MVME5100 Single Board Computer Programmer's Reference Guide

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1 Product Data and Memory Maps IDREQ_ LLB3_ MODSEL Table 1-21. Interpretation of MID3-MID0 MID3 MID2 MID1 MID0 0 1 0 0 1 1 Module 3: EIA530 DTE 01-W3879B01 0 1 1 1 1 1 Module 4 Not Installed Serial Module Type Module Assembly Number Note Because IDREQ_ and MID3-MID0 signals go through the P2MX (P2 multiplexing) function used on <strong>MVME5100</strong> series boards configured for the MVME761-type transition module, software must wait for the MID3-MID0 to become valid after asserting IDREQ_. The waiting time should be about 4 microseconds because the sampling rate is about 1.6 microsecond with a 10MHz MXCLK clock. 1-38 <strong>Computer</strong> Group Literature Center Web Site
ISA DMA Channels PIB Priority IPMC7xx ISA Bus Resources There are seven ISA DMA channels in the PIB. Channels 0 through 3 support only 8-bit DMA devices while Channels 5 through 7 support only 16-bit DMA devices. These DMA channels are assigned as follows: Table 1-22. PIB DMA Channel Assignments PIB Label Controller DMA Assignment Highest Channel 0 DMA1 Serial Port 3 Receiver (Z85230 Port A Rx) Channel 1 Serial Port 3 Transmitter (Z85230 Port A Tx) Channel 2 Floppy Drive Controller Channel 3 Parallel Port Channel 4 DMA2 Not available - Cascaded from DMA1 Channel 5 Serial Port 4 Receiver (Z85230 Port B Rx) Channel 6 Serial Port 4 Transmitter (Z85230 Port B Tx) Lowest Channel 7 Not Used Note Because the Z85230 is an 8-bit device and Channels 5 and 6 are 16-bit DMA Channels, only every other byte (the even bytes) from memory is valid. http://www.motorola.com/computer/literature 1-39 1
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
Page 15: List of Figures Figure 1-1. MVME510
Page 18 and 19: xviii Table 2-13. Address Modificat
Page 21 and 22: About This Manual The MVME5100 Sing
Page 23 and 24: Part Number Description MVME761-011
Page 25 and 26: 8259 Interrupts, and a description
Page 27: In this manual, assertion and negat
Page 30 and 31: 1 Product Data and Memory Maps Main
Page 32 and 33: 1 Product Data and Memory Maps Memo
Page 34 and 35: 1 Product Data and Memory Maps Tabl
Page 36 and 37: 1 Product Data and Memory Maps PCI
Page 38 and 39: 1 Product Data and Memory Maps L2 C
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Page 42 and 43: 1 Product Data and Memory Maps to i
Page 44 and 45: 1 Product Data and Memory Maps Requ
Page 46 and 47: 1 Product Data and Memory Maps PROC
Page 48 and 49: 1 Product Data and Memory Maps The
Page 50 and 51: 1 Product Data and Memory Maps Tabl
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Page 54 and 55: 1 Product Data and Memory Maps MODR
Page 56 and 57: 1 Product Data and Memory Maps NVRA
Page 58 and 59: 1 Product Data and Memory Maps Geog
Page 60 and 61: 1 Product Data and Memory Maps Boar
Page 62 and 63: 1 Product Data and Memory Maps IPMC
Page 64 and 65: 1 Product Data and Memory Maps Z853
Page 69 and 70: 2Hawk PCI Host Bridge & Multi- Proc
Page 71 and 72: Block Diagram PCI Bus MPIC Interfac
Page 73 and 74: PPC Bus Interface Functional Descri
Page 75 and 76: PPC Slave Functional Description Ea
Page 77 and 78: PPC FIFO PPC Transfer Type Transfer
Page 79 and 80: Functional Description Table 2-2. P
Page 81 and 82: Table 2-4. PPC Master Read Ahead Op
Page 83 and 84: PPC Arbiter Pin Name Functional Des
Page 85 and 86: PPC Parity Functional Description T
Page 87 and 88: PCI Bus Interface PCI Address Mappi
Page 89 and 90: Functional Description Each map dec
Page 91 and 92: Command Types: Functional Descripti
Page 93 and 94: Fast Back-to-Back Transactions Func
Page 95 and 96: Functional Description It should be
Page 97 and 98: Functional Description The PCI Mast
Page 99 and 100: . Figure 2-6. PCI Spread I/O Addres
Page 101 and 102: Functional Description The device t
Page 103 and 104: Functional Description The Hawk’s
Page 105 and 106: Functional Description Notes 1. “
Page 107 and 108: . DH07-00 DH15-08 DH23-16 DH31-24 F
Page 109 and 110: Error Handling Functional Descripti
Page 111 and 112: Functional Description When not bei
Page 113 and 114: Functional Description PPC1-Bug>md
Page 115 and 116: Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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