MVME5100 Single Board Computer Programmer's Reference Guide

Timer Vector/Priority Registers
Offset Timer 0 - $01120
Timer 1 - $01160
Timer 2 - $011A0
Timer 3 - $011E0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
Name TIMER VECTOR/PRIORITY
Operation
Reset
ACT
MASK
R
R/W
0
1
2
2
2
1
2
0
1
9
1
8
Registers
MASK MASK. Setting this bit disables any further interrupts
from this source. If the mask bit is cleared while the bit
associated with this interrupt is set in the IPR, the interrupt
request will be generated.
ACT ACTIVITY. The activity bit indicates that an interrupt
has been requested or that it is in-service. The ACT bit is
set to a one when its associated bit in the Interrupt Pending
Register or In-Service Register is set.
PRIOR PRIORITY. Interrupt priority 0 is the lowest and 15 is
the highest. Note that a priority level of 0 will not enable
interrupts.
VECTOR VECTOR. This vector is returned when the Interrupt
Acknowledge register is examined upon acknowledgment
of the interrupt associated with this vector.
http://www.motorola.com/computer/literature 2-121
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
PRIOR VECTOR
R R/W R R/W
$000 $0 $00 $00
2