MVME5100 Single Board Computer Programmer's Reference Guide

Functional Description
Table 2-2. PPC Master Transaction Profiles and Starting Offsets
Start Offset
(i.e. from 0x00,0x20,0x40,etc.)
0x...00 -> 0x....07 Burst @ 0x00
Burst @ 0x20
....
0x....08 -> 0x....0f Single @ 0x08
Single @ 0x10
Single @ 0x18
Burst @ 0x20
....
0x....10 -> 0x....17 Single @ 0x10
Single @ 0x18
Burst @ 0x20
....
0x....18 -> 0x....1f Single @ 0x18
Burst @ 0x20
....
Write Profile Read Profile Notes
Burst @ 0x00
Burst @ 0x20
....
Burst @ 0x00
Burst @ 0x20
....
Burst @ 0x00
Burst @ 0x20
....
Single @ 0x18
Burst @ 0x20
....
Most efficient
Discard read beat 0x00
Discard read beat 0x00
and 0x08
While the PCI Slave is filling the PCI FIFO with write data, the PPC
Master can be moving previously posted write data onto the PPC60x bus.
In general, the PPC60x bus is running at a higher clock rate than the PCI
bus, which means the PCI bus can transfer data at a continuous
uninterrupted burst while the PPC60x bus transfers data in distributed
multiple bursts. The PHB write posting mechanism has been tuned to
create the most efficient possible data transfer between the two busses
during typical operation. It is conceivable that some non-typical conditions
could exist that would upset the default write post tuning of the PHB. For
example, if a PPC60x master is excessively using PPC60x bus bandwidth,
then the additional latency associated with obtaining ownership of the
PPC60x bus might cause the PCI Slave to stall if the PCI FIFO gets full. If
the PCI Slave is continuously stalling during write posted transactions,
then further tuning might be needed. This can be accomplished by
changing the WXFT (Write Any Fifo Threshold) field within the PSATTx
registers to recharacterize PHB write posting mechanism. The FIFO
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