MVME5100 Single Board Computer Programmer's Reference Guide

Current Task Priority Registers
Offset Processor 0 $20080
Processor 1 $21080
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
Registers
There is one Task Priority Register per processor. Priority levels from 0
(lowest) to 15 (highest) are supported. Setting the Task Priority Register to
15 masks all interrupts to this processor. Hardware will set the task register
to $F when it is reset or when the Init bit associated with this processor is
written to a one.
Interrupt Acknowledge Registers
2
0
1
9
1
8
TP Task Priority of processor.
On PowerPC-based systems, Interrupt Acknowledge is implemented as a
read request to a memory-mapped Interrupt Acknowledge register.
Reading the Interrupt Acknowledge register returns the interrupt vector
corresponding to the highest priority pending interrupt. Reading this
register also has the following side effects. Reading this register without a
pending interrupt will return a value of $FF hex.
❏ The associated bit in the Interrupt Pending Register is cleared.
❏ Reading this register will update the In-Service register.
VECTOR Vector. This vector is returned when the Interrupt
Acknowledge register is read.
http://www.motorola.com/computer/literature 2-127
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name CURRENT TASK PRIORITY
Operation R R R R
TP
R/W
Reset $00 $00 $00 $0 $F
Offset Processor 0 $200A0
Processor 1 $210A0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name VECTOR
Operation R R R R
Reset $00 $00 $00 $FF
2