MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Timer Basecount Registers
Offset Timer 0 - $01110
Timer 1 - $01150
Timer 2 - $01190
Timer 3 - $011D0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
Name TIMER BASECOUNT
Operation
Reset
CI
R/W
1
2
3
2
2
2
1
2
0
1
9
1
8
CI COUNT INHIBIT. Setting this bit to one inhibits
counting for this timer. Setting this bit to zero allows
counting to proceed.
BC BASE COUNT. This field contains the 31 bit count for
this timer. When a value is written into this register and
the CI bit transitions from a 1 to a 0, it is copied into the
corresponding Current Count register and the toggle bit in
the Current Count register is cleared. When the timer
counts down to zero, the Current Count register is
reloaded from the Base Count register and the timer’s
interrupt becomes pending in MPIC processing.
2-120 Computer Group Literature Center Web Site
1
7
1
6
1
5
BC
R/W
1
4
1
3
$00000000
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0