MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
Writes that change these bits must be enveloped by a
period of time in which no accesses to ROM/Flash Block
A, occur. A simple way to provide the envelope is to
perform at least two accesses to this or another of the
SMC’s registers before and after the write.
Table 3-15. ROM Speed Bit Encodings
rom_a/b_spd0,1 Approximate ROM Block A/B Device Access Time
%00 12 Clock Periods (120ns @ 100 MHz, 180ns @ 66.67 MHz)
%01 8 Clock Periods (80ns @ 100 MHz, 120ns @ 66.67 MHz)
%10 5 Clock Periods (50ns @ 100 MHz, 75ns @ 66.67 MHz)
%11 3 Clock Periods (30ns @100 MHz, 45ns @ 66.67 MHz)
rom_b_spd0,1 rom_b_spd0,1 determine the access timing used for
ROM/Flash Block B. Refer to the table above.
Writes that change these bits must be enveloped by a
period of time in which no accesses to ROM/Flash, Bank
B, occur. A simple way to provide the envelope is to
perform at least two accesses to this or another of the
SMC’s registers before and after the write.
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