MVME5100 Single Board Computer Programmer's Reference Guide

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Summary of Changes xxiv The following changes were made for the 2nd revision of this manual. Date Doc. Rev Changes 09/2001 V5100A/PG2 Memory Maps and additional register information was added to Chapter 1. Corrections were made to Table 4-1 in Chapter 4. Additions were made to Appendix A, Releated Documentation. Appendix B, VPD Information was added. This section titled "About this Manual" was also added. 07/2003 v5100A/PG3 Added information at the end of Chapter 1 on IPMC7xx ISA Bus Resources. Corrected incorrect address for DS1621 SROM. Added Appendix C, VMEbus Mapping Example. Added corrections/additions for CLK_FREQUENCY Register in Chapter 3. Overview of Contents The following paragraphs briefly describe the contents of each chapter. Chapter 1, Product Data and Memory Maps, provides a description of the MVME5100, tables of specific memory maps and other control registers. Chapter 2, Hawk PCI Host Bridge & Multi-Processor Interrupt Controller, provides a description of the Hawk’s PowerPC to Local Bus Bridge (PHB) and the Multi-Processor Interrupt Controller (MPIC) including a list of features, a block diagram, a functional description and corresponding register tables. Chapter 3, System Memory Controller (SMC), provides an explanation of the System Memory Controller (SMC) portion of the Hawk ASIC including a features list, block diagrams, functional descriptions, and an explanation and description of all corresponding registers. Chapter 4, Hawk Programming Details, procides a summary of the Hawk programming details that are relevant to every day programming functions, including a listing of the Hawk MPIC External Interrupts, the
8259 Interrupts, and a description of certain exceptions such as sources of reset, error notification and handling, endian issues, and processor/Hawk relationships. Appendix A, Related Documentation, provides a listing of related Motorola manuals, vendor documentation and industry specifications. Appendix B, MVME5100 VPD Reference Information, provides an explanation of the VPD reference information including certain "How to" info, as well as specific VPD Data Definitions. Appendix C, VMEbus Mapping Example, provides an example of a mapping scenario between an MVME5100 and an MVME2700 on a VMEbus backplane. Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to: Motorola Computer Group Reader Comments DW164 2900 S. Diablo Way Tempe, Arizona 85282 You can also submit comments to the following e-mail address: reader-comments@mcg.mot.com In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements. Conventions Used in This Manual The following typographical conventions are used in this document: bold xxv
Page 1 and 2: MVME5100 Single Board Computer Prog
Page 3 and 4: Safety Summary The following genera
Page 5 and 6: CE Notice (European Community) Moto
Page 7 and 8: Contents About This Manual Summary
Page 9 and 10: PCI Slave .........................
Page 11 and 12: Spurious Vector Register...........
Page 13 and 14: Address Parity Error Log Register .
Page 15: List of Figures Figure 1-1. MVME510
Page 18 and 19: xviii Table 2-13. Address Modificat
Page 21 and 22: About This Manual The MVME5100 Sing
Page 23: Part Number Description MVME761-011
Page 27: In this manual, assertion and negat
Page 30 and 31: 1 Product Data and Memory Maps Main
Page 32 and 33: 1 Product Data and Memory Maps Memo
Page 34 and 35: 1 Product Data and Memory Maps Tabl
Page 36 and 37: 1 Product Data and Memory Maps PCI
Page 38 and 39: 1 Product Data and Memory Maps L2 C
Page 40 and 41: 1 Product Data and Memory Maps conn
Page 42 and 43: 1 Product Data and Memory Maps to i
Page 44 and 45: 1 Product Data and Memory Maps Requ
Page 46 and 47: 1 Product Data and Memory Maps PROC
Page 48 and 49: 1 Product Data and Memory Maps The
Page 50 and 51: 1 Product Data and Memory Maps Tabl
Page 52 and 53: 1 Product Data and Memory Maps Stat
Page 54 and 55: 1 Product Data and Memory Maps MODR
Page 56 and 57: 1 Product Data and Memory Maps NVRA
Page 58 and 59: 1 Product Data and Memory Maps Geog
Page 60 and 61: 1 Product Data and Memory Maps Boar
Page 62 and 63: 1 Product Data and Memory Maps IPMC
Page 64 and 65: 1 Product Data and Memory Maps Z853
Page 66 and 67: 1 Product Data and Memory Maps IDRE
Page 69 and 70: 2Hawk PCI Host Bridge & Multi- Proc
Page 71 and 72: Block Diagram PCI Bus MPIC Interfac
Page 73 and 74: PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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