MVME5100 Single Board Computer Programmer's Reference Guide

SDRAM Organization
Functional Description
The SDRAM is organized as 1, 2, 3, 4, 5, 6, 7, or 8 blocks, 72 bits wide
with 64 of the bits being normal data and the other 8 being checkbits. The
72 bits of SDRAM for each block can be made up of x4, x8, or x16
components or of 72-bit DIMMs that are made up of x4 or x8 components.
The 72-bit, unbuffered DIMMs can be used as long as AC timing is met
and they use the components listed. All components must be organized
with 4 internal banks.
PPC60x Bus Interface
The SMC has a PowerPC slave interface only. It has no PowerPC master
interface. The slave interface is the mechanism for all accesses to
SDRAM, ROM/Flash, and the internal and external register sets.
Responding to Address Transfers
Completing Data Transfers
When the SMC detects an address transfer that it is to respond to, it asserts
AACK_ immediately if there is no uncompleted PPC60x bus data transfer
in process. If there is one in process, then the SMC waits and asserts
AACK_ coincident with the uncompleted data transfer’s last data beat if
the SMC is the slave for the previous data. If it is not, it holds off AACK_
until the CLK after the previous data transfer’s last data beat.
If an address transfer to the SMC will have an associated data transfer, the
SMC begins a read or write cycle to the accessed entity
(SDRAM/ROM/Flash/Internal or External Register) as soon as the entity
is free. If the data transfer will be a read, the SMC begins providing data
to the PPC60x bus as soon as the entity has data ready and the PPC60x data
bus is granted. If the data transfer will be a write, the SMC begins latching
data from the PowerPC data bus as soon as any previously latched data is
no longer needed and the PPC60x data bus is available.
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