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MVME5100 Single Board Computer Programmer's Reference Guide

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Registers<br />

INV Invalidate Enable. If set, the PPC Master will issue a<br />

transfer type code which specifies the current transaction<br />

should cause an invalidate for each PPC transaction<br />

originated by the corresponding PCI Slave. The transfer<br />

type codes generated are shown in Table 2-5 on page 2-14.<br />

GBL Global Enable. If set, the PPC Master will assert the<br />

GBL_ pin for each PPC transaction originated by the<br />

corresponding PCI Slave.<br />

RAEN Read Ahead Enable. If set, read ahead is enabled for the<br />

corresponding PCI Slave.<br />

WPEN Write Post Enable. If set, write posting is enabled for the<br />

corresponding PCI Slave.<br />

WEN Write Enable. If set, the corresponding PCI Slave is<br />

enabled for write transactions.<br />

REN Read Enable. If set, the corresponding PCI Slave is<br />

enabled for read transactions.<br />

RMFTx Read Multiple FIFO Threshold. This field is used by the<br />

PHB to determine a FIFO threshold at which to continue<br />

prefetching data from local memory during PCI read<br />

multiple transactions. This threshold applies to<br />

subsequent prefetch reads since all initial prefetch reads<br />

will be four cache lines. This field is only applicable if<br />

read-ahead has been enabled. The encoding of this field is<br />

shown in the table below.<br />

RMFT/RXFT Subsequent Prefetch FIFO Threshold<br />

00 0 Cache lines<br />

01 1 Cache line<br />

10 2 Cache lines<br />

11 3 Cache lines<br />

RXFTx Read Any FIFO Threshold. This field is used by the<br />

PHB to determine a FIFO threshold at which to continue<br />

prefetching data from local memory during PCI read and<br />

read line transactions. This threshold applies to<br />

subsequent prefetch reads since all initial prefetch reads<br />

http://www.motorola.com/computer/literature 2-105<br />

2

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