MVME5100 Single Board Computer Programmer's Reference Guide

3System Memory Controller
(SMC)
Introduction
Overview
3
The SMC in the Hawk ASIC is equivalent to the former Falcon Pair
portion of a Falcon/Raven chipset. The SMC has interfaces between the
PPC60x bus and SDRAM, ROM/Flash, and its Control and Status Register
sets (CSR). Note that the term SDRAM refers to Synchronous Dynamic
Random Access Memory and is used throughout this document.
This chapter provides a functional description and programming model for
the SMC portion of the Hawk. Most of the information for using the device
in a system, programming it in a system, and testing it, is contained here.
Bit Ordering Convention
Features
All SMC bused signals are named using Big-Endian bit ordering (bit 0 is
the most significant bit), except for the RA signals, which use Little-
Endian bit ordering (bit 0 is the least significant bit).
❏ SDRAM Interface
– Double-bit error detect/Single-bit error correct on 72-bit basis.
– Two blocks with up to 256MB each at 100 MHz.
– Eight blocks with up to 256MB each at 66.67 MHz
– Uses -8, -10, or PC100 SDRAMs
– Programmable base address for each block.
– Built-in Refresh/Scrub.
❏ Error Notification for SDRAM
– Software programmable Interrupt on Single/Double-Bit Error.
– Error address and Syndrome Log Registers for Error Logging.
– Does not provide TEA_ on Double-Bit Error. (Chip has no
TEA_ pin.)
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