MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Timer Destination Registers
Offset Timer 0 - $01130
Timer 1 - $01170
Timer 2 - $011B0
Timer 3 - $011F0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
This register indicates the destinations for this timer’s interrupts. Timer
interrupts operate in the Directed delivery interrupt mode. This register
may specify multiple destinations (multicast delivery).
P1 PROCESSOR 1. The interrupt is directed to processor 1.
P0 PROCESSOR 0. The interrupt is directed to processor 0.
External Source Vector/Priority Registers
2
5
2
4
Name TIMER DESTINATION
2
3
2
2
2
1
2
0
1
9
1
8
2-122 Computer Group Literature Center Web Site
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Operation R R R R
Reset $00 $00 $00 $00 0
Offset Int Src 0 - $10000
Int Src 1-> Int Src15 - $10020 -> $101E0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
Name EXTERNAL SOURCE VECTOR/PRIORITY
Operation
Reset
ACT
MASK
R
R/W
0
1
R
$000
SENSE
POL
2
1
2
0
R
R
R/W
R/W
0
0
0
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
P0
P1
R/W
R/W
0
1
0 9 8 7 6 5 4 3 2 1 0
PRIOR VECTOR
R/W R R/W
$0 $00 $00