MVME5100 Single Board Computer Programmer's Reference Guide

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3 System Memory Controller (SMC) Register Summary BIT # ----> Table 3-9 shows a summary of the internal and external register set. 0 1 2 3 4 5 Table 3-9. Register Summary 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FEF80000 VENDID DEVID FEF80008 FEF80010 ram a en RAM A SIZ tben_en ram b en REVID RAM B SIZ 3-36 <strong>Computer</strong> Group Literature Center Web Site ram c en aonly_en isa_hole RAM C SIZ FEF80018 RAM A BASE RAM B BASE RAM C BASE RAM D BASE ram d en PU STAT RAM D SIZ FEF80020 CLK FREQUENCY por FEF80028 FEF80030 elog refdis rwcb derc escb esen embt esbt apien scien dpien sien ERR_SYNDROME mien int FEF80038 ERROR_ADDRESS FEF80040 scb0 scb1 swen esblk0 esblk1 esblk2 FEF80048 SCRUB ADDRESS FEF80050 FEF80058 FEF80060 FEF80068 dpelog ROM A BASE ROM B BASE rom_a_64 rom_b_64 DPE_TT DPE_DP ROM A SIZ ROM B SIZ scof dpe_ckall dpe_me SBE COUNT SCRUB FREQUENCY rom_a_spd0 rom_a_spd1 GWDP mbe_me rom_a_rv rom a en rom a we rom_b_rv rom b en rom b we rom_b_spd0 rom_b_spd1
FEF80070 DPE_A FEF80078 DPE_DH FEF80080 DPE_DL FEF80090 I2_PRESCALE_VAL FEF80098 FEF800A0 Programming Model i2_start i2_stop i2_ackout http://www.motorola.com/computer/literature 3-37 i2_enbl i2_datin i2_err i2_ackin i2_cmplt FEF800A8 I2_DATAWR FEF800B0 I2_DATARD FEF800C0 ram e en RAM E SIZ ram f en RAM F SIZ ram g en RAM G SIZ FEF800C8 RAM E BASE RAM F BASE RAM G BASE RAM H BASE FEF800D0 FEF800E0 apelog cl3 trc0 trc1 trc2 tras0 tras1 swr_dpl tdp APE_TT APE_AP FEF800E8 APE_A FEF80100 CTR32 FEF88300 FEF88000 - FEF8FFF8 BIT # ----> 0 p1_tben p0_tben Table 3-9. Register Summary (Continued) 1 2 3 4 5 6 7 8 9 10 trp EXTERNAL REGISTER SET trcd ape_me ram h en RAM H SIZ 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 3
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
Page 181 and 182: 3 1 3 0 2 9 2 8 2 7 Feature Reporti
Page 183 and 184: Registers M CASCADE MODE. Allows ca
Page 185 and 186: IPI Vector/Priority Registers Offse
Page 187 and 188: Timer Current Count Registers Offse
Page 189 and 190: Timer Vector/Priority Registers Off
Page 191 and 192: Registers MASK MASK. Setting this b
Page 193 and 194: Hawk Internal Error Interrupt Vecto
Page 195 and 196: Current Task Priority Registers Off
Page 197 and 198: 3System Memory Controller (SMC) Int
Page 199 and 200: PowerPC Side D[0:63] DP[0:7] Correc
Page 201 and 202: Figure 3-4. Hawk’s System Memory
Page 203 and 204: Page Holding SDRAM Speeds Functiona
Page 205 and 206: SDRAM Organization Functional Descr
Page 207 and 208: Cache Coherency Functional Descript
Page 209 and 210: Error Logging Functional Descriptio
Page 211 and 212: Functional Description When the wid
Page 213 and 214: Table 3-4. PPC60x to ROM/Flash (64
Page 215 and 216: ROM/Flash Speeds ACCESS TYPE Functi
Page 217 and 218: ACCESS TYPE Functional Description
Page 219 and 220: I 2 C Byte Write Functional Descrip
Page 221 and 222: I 2 C Random Read Functional Descri
Page 223 and 224: I 2 C Current Address Read Function
Page 225 and 226: I 2 C Page Write Functional Descrip
Page 227 and 228: I 2 C Sequential Read Functional De
Page 229 and 230: SDA START DEVICE ADDR M S B BEGIN R
Page 231: Chip Configuration Programming Mode
Page 235 and 236: Vendor/Device Register Address $FEF
Page 237 and 238: SDRAM Enable and Size Register (Blo
Page 239 and 240: SDRAM Base Address Register (Blocks
Page 241 and 242: drr value Programming Model us (64
Page 243 and 244: Normal View of Data (rwcb=0) Check-
Page 245 and 246: ! Caution Programming Model sien Wh
Page 247 and 248: Programming Model esbt esbt is set
Page 249 and 250: Scrub Address Register Programming
Page 251 and 252: Programming Model each half of the
Page 253 and 254: ROM B Base/Size Register Address Bi
Page 255 and 256: ROM Speed Attributes Registers Prog
Page 257 and 258: Data Parity Error Log Register Addr
Page 259 and 260: Data Parity Error Lower Data Regist
Page 261 and 262: I 2 C Status Register Programming M
Page 263 and 264: I 2 C Receiver Data Register Addres
Page 265 and 266: SDRAM Speed Attributes Register Pro
Page 267 and 268: Programming Model swr_dpl swr_dpl c
Page 269 and 270: 32-Bit Counter Address $FEF80100 Bi
Page 271 and 272: Software Considerations When the tb
Page 273 and 274: SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276: Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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