MVME5100 Single Board Computer Programmer's Reference Guide

Registers
XBTOI PPC Address Bus Time-out Interrupt Enable. When
this bit is set, the XBTO bit in the MERST register will be
used to assert an interrupt through the MPIC interrupt
controller. When this bit is clear, no interrupt will be
asserted.
XDPEI PPC Data Parity Error Interrupt Enable. When this bit
is set, the XDPE bit in the ESTAT register will be used to
assert an interrupt through the MPIC. When this bit is
clear, no interrupt will be asserted.
PPERI PCI Parity Error Interrupt Enable. When this bit is set,
the PPER bit in the ESTAT register will be used to assert
an interrupt through the MPIC interrupt controller. When
this bit is clear, no interrupt will be asserted.
PSERI PCI System Error Interrupt Enable. When this bit is
set, the PSER bit in the ESTAT register will be used to
assert an interrupt through the MPIC interrupt controller.
When this bit is clear, no interrupt will be asserted.
PSMAI PCI Master Signalled Master Abort Interrupt Enable.
When this bit is set, the PSMA bit in the ESTAT register
will be used to assert an interrupt through the MPIC
interrupt controller. When this bit is clear, no interrupt will
be asserted.
PRTAI PCI Master Received Target Abort Interrupt Enable.
When this bit is set, the PRTA bit in the ESTAT register
will be used to assert an interrupt through the MPIC
interrupt controller. When this bit is clear, no interrupt will
be asserted.
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