MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
PPC Master
For example, two burst transactions make the data FIFO the limiting factor
for write posting. Four single beat transactions make the command FIFO
the limiting factor. If either limit is exceeded, then any pending PPC
transactions is delayed (AACK_ and TA_ are not asserted) until the PCI
Master has completed a portion of the previously posted transactions and
created some room within the command and/or data FIFOs.
The PHB does not support byte merging or byte collapsing. Each and
every single beat transaction presented to the PPC Slave is presented to the
PCI bus as a unique single beat transfer.
The PPC Master can transfer data either in 1-to-8 byte single beat
transactions or 32 byte, four beat burst transactions. This limitation is
strictly imposed by the PPC60x bus protocol. The PPC Master attempts to
move data using burst transfers whenever possible. If a transaction starts
on a non-cache line address, the PPC Master performs as many single beat
transactions as needed until the next highest cache line boundary is
reached. If a write transaction ends on a non-cache line boundary, then the
PPC Master finishes the transaction with as many single beat transactions
as needed to complete the transaction.
Table 2-2 shows the relationship between the starting addresses and the
PPC60x bus transaction types when write posting and read ahead are
enabled.
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