MVME5100 Single Board Computer Programmer's Reference Guide

PPC Parity
Functional Description
The PHB generates data parity whenever it is sourcing PPC data. This
happens during PPC Master write cycles and PPC Slave read cycles. Valid
data parity is presented when DBB_ is asserted for PPC Master write
cycles. Valid data parity is presented when TA_ is asserted for PPC Slave
read cycles.
The PHB checks data parity whenever it is sinking PPC data. This happens
during PPC Master read cycles and PPC Slave write cycles. Data parity is
considered valid anytime TA_ has been asserted. If a data parity error is
detected, then the PHB will latch address and attribute information within
the ESTAT, EADDR, and EATTR registers, and an interrupt or machine
check will be generated depending on the programming of the ESTAT
register.
The PHB has a mechanism to purposely induce data parity errors for
testability. The DPE field within the ETEST register can be used to
purposely inject data parity errors on specific data parity lines. Data parity
errors can only be injected during cycles where PHB is sourcing PPC data.
The PHB will generate address parity whenever it is sourcing a PPC
address. This will happen for all PPC Master transactions. Valid address
parity will be presented when ABB_ is being asserted.
The PHB has a mechanism to purposely inject address parity errors for
testability. The APE field within the ETEST register can be used to
purposely inject address parity errors on specific address parity lines.
Address parity errors can only be injected during cycles where PHB is
sourcing a PPC address.
The PHB does not have the ability to check for address parity errors.
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