MVME5100 Single Board Computer Programmer's Reference Guide

ROM B Base/Size Register
Address
Bit
$FEF80058
Name ROM B BASE
5
4
3
2
1
0
7
6
Operation READ/WRITE
Reset $FF4 PL
10
9
8
12
11
14
13
16
15
rom b siz2
rom b siz1
rom b siz0
rom_b_64
R/W
R/W
R/W
R
0 PL
0 PL
0 PL
V P
18
17
20
19
READ ZERO
22
21
Programming Model
24
23
26
25
28
27
30
29
Writes to this register must be enveloped by a period of time in which no
accesses to ROM/Flash Block B, occur. A simple way to provide the
envelope is to perform at least two accesses to this (or another of the
SMC’s registers before and after the write).
ROM B BASE These control bits define the base address for ROM/Flash
Block B. ROM B BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash
sizes, the lower significant bits of ROM B BASE are
ignored. This means that the block’s base address will
always appear at an even multiple of its size. ROM B
BASE is initialized to $FF4 at power-up or local bus reset.
Note that in addition to the programmed address, the first
1Mbyte of Block B also appears at $FFF00000 -
$FFFFFFFF if the rom_b_rv bit is set.
Also note that the combination of ROM_B_BASE and
rom_b_siz should never be programmed such that
ROM/Flash Block B responds at the same address as the
CSR, SDRAM, External Register Set, or any other slave
on the PowerPC bus.
http://www.motorola.com/computer/literature 3-57
X
31
rom b we
rom b en
rom_b_rv
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
0 PL
0 PL
V P
X
X
X
X
X
3