MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Watchdog Timers
When any bit in the ESTAT is set, the PHB will attempt to latch as much
information as possible about the error in the PPC Error Address
(EADDR) and Attribute Registers (EATTR). Information is saved as
follows:
Error
Status
XBTO From PPC bus
XDPE From PPC bus
PRTA From PCI bus
PSMA From PCI bus
PPER Invalid
PSER Invalid
Error Address and
Attributes
Each ESTAT error bit may be programmed to generate a machine check
and/or a standard interrupt. The error response is programmed through the
PPC Error Enable Register (EENAB) on a source by source basis. When a
machine check is enabled, either the XID field in the EATTR Register or
the DFLT bit in the EENAB Register determines the master to which the
machine check is directed. For errors in which the master who originated
the transaction can be determined, the XID field is used. For errors not
associated with a particular PPC master, or associated with masters other
than processor 0,1 or 2, the DFLT bit is used. One example of an error
condition which cannot be associated with a particular PPC master would
be a PCI system error.
PHB features two watchdog timers called Watchdog Timer 1 (WDT1) and
Watchdog Timer 2 (WDT2). Although both timers are functionally
equivalent, each timer operates completely independent of each other.
WDT1 and WDT2 are initialized at reset to a count value of 8 seconds and
16 seconds respectively. The timers are designed to be reloaded by
software at any time.
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