MVME5100 Single Board Computer Programmer's Reference Guide

Functional Description
From the perspective of the PCI bus, a better solution would be to select a
PCI FIFO threshold that will allow the bridge lock resolution cycle to
happen early enough to keep the PCI FIFO from getting filled. A similar
case exists with regard to PCI read cycles. Having the bridge lock
resolution associated with a particular PCI FIFO threshold would allow the
PPC Master to get an early enough start at prefetching read data to keep the
PCI Slave from starving for read data.
From the perspective of the PPC bus, a selective FIFO threshold will make
the PPC Slave release the PPC bus at an earlier time thereby reducing
wasted PPC bus bandwidth. PHB offers an option to have the PPC Slave
remove a stalled transaction immediately upon detecting any PCI Slave
activity. This option would help in the case where distributing PPC60x bus
bandwidth between multiple masters is of the utmost importance.
The PHB is tuned to provide the most efficient solution for bridge lock
resolution under normal operating conditions. If further fine tuning is
desired, the WLRT/RLRT (Write Lock Resolution Threshold/Read Lock
Resolution Threshold) fields within the HCSR can be adjusted
accordingly. Note that the FIFO full option exists mainly to remain
architecturally backwards compatible with previous bridge designs.
Speculative PCI Request
There is a case where the processor could get starved for PCI read data
while the PCI Slave is hosting multiple PPC60x bound write cycles. While
attempting to perform a read from PCI space, the processor would
continually get retried as a result of bridge lock resolution.
Between PCI writes, the PPC Master will be taking PPC60x bus bandwidth
trying to empty write posted data, which will further hamper the ability of
the processor to complete its read transaction.
PHB offers an optional speculative PCI request mode that helps the
processor complete read cycles from PCI space. If a bridge lock resolution
cycle happens when the PPC Slave is hosting a compelled cycle, the PCI
Master will speculatively assert a request on the PCI bus. Sometime later
when the processor comes back and retries the compelled cycle, the results
of the PCI Master holding will increase the chance of the processor
successfully completing its cycle.
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