MVME5100 Single Board Computer Programmer's Reference Guide

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I N D E X Global Configuration Register 2-114 H Hardware Control-Status Register 2-77 Hawk address parity 3-10 as MPU/PCI bus bridge controller ASIC 1-15 block diagram 2-3 configuration options 3-35 data parity 3-10 ECC Codes 3-87 Error Correction Codes 3-87 error notification and handling 4-6 I2C Byte Write 3-23 I2C Current Address Read 3-27 I2C Page Write 3-29 I2C Random Read 3-25 I2C Sequential Read 3-31 MPIC control registers 2-22 MPIC interrupt assignments 4-1 MPIC interrupts 4-1 MPIC register map 2-110 PCI Host Bridge & Multi-Processor Interrupt Controller chip 2-1 programming details 4-1 programming ROM/Flash devices 3-75 SMC 3-1 software considerations 3-75 System Memory Controller block diagram 3-3 used with DRAM in a system 3-2 writing to the control registers 3-75 Hawk ASIC 1-12 Hawk External Register Bus Summar 1-21 Hawk I2C interface and configuration information 1-13 Hawk PCI Host Bridge 1-2 Hawk System Memory Controller 1-2 Hawk’s DEVSEL_ pin as criteria for PHB config. mapping 2-19 Hawk’s I2C bus 3-77 Index Hawk’s PCI arbiter priority schemes 2-35 Hawk’s SMC overview 3-1 HCSR Hardware Control-Status Register 2-77 Header/Type Register 2-101 I I/O Base Register MPIC 2-102 I2C Byte Write, Hawk 3-23 Current Address Read, Hawk 3-27 EEPROMs 3-77 Page Write, Hawk 3-29 Random Read, Hawk 3-25 Sequential Read, Hawk 3-31 I2C Receiver Data Register 3-67 IDSEL Mapping for PCI Devices 1-19 initializing SDRAM-related control registers 3-76 Inter-Integrated Circuit 1-13 Internal Clock Frequency 1-1 interpretation of MID3-MID0 1-37 Interprocessor Interrupt Dispatch Registers 2-126 Interrupt Acknowledge Registers 2-127 Interrupt Controller 1-2 features 2-2 Interrupt Enable control bits 3-48 interrupts 8259 4-3 Hawk MPIC 4-1 introduction 1-1 Hawk PHB/MPIC 2-1 PHB/MPIC 2-1 programming details for Hawk 4-1 SMC 3-1 IPI Vector/Priority Registers 2-117 IN-4 Computer Group Literature Center Web Site
L L2 Cache 1-1, 1-9 L2 Cache SRAM Size 1-10 L2 cache support SMC 3-11 L2CLK bits 1-10 L2CLM_ 3-11 latency PCI Slave 2-25 Little Endian mode of PPC devices 2-39 little-endian mode 4-8 Lock Resolution programmable 2-46 M Main Memory 1-2 map decoders PPC to PCI 2-7 mapping PPC address 2-6 master initiated termination 2-28 mcken 3-49 memory ECC 1-11 Memory Base Register 2-102 Memory Controller 1-2 memory map CHRP 1-5 PCI local bus 1-4, 1-8 processor (default) 1-4 Memory maps 1-4 memory maps 1-4 VMEbus 1-8 Memory Subsystem Data 1-13 mien 3-49 Miscellaneous MVME5100 features 1-2 MODFAIL Bit Register 1-25 MODRST Bit Register 1-26 MPC arbiter 2-15 MPC bus address space 2-19 MPC slave 2-7 MPC slave response command types 2-8 MPC to PCI address decoding 2-6 MPC750 processor/memory domain 4-9 MPIC 2-1 interface with PHB 2-5 MPIC Registers 2-110 MPIC registers 2-110 MPIC’s involvement 4-9 Multi-Processor Interrupt Controller 2-1 MVME Key Features 1-1 MVME5100 endian issues 4-7 sources of reset 4-5 MVME5100 Block Diagram 1-3 MVME510x VME Processor Module 1-1 N NVRAM 1-2 NVRAM/RTC & Watchdog Timer 1-34 O overview 2-1 SMC 3-1 P P2 I/O modes 1-11 parity 2-29 PCI Slave 2-25 Parity checking 1-9 PC100 ECC 1-2 PCI address mapping 2-19 arbiter, Hawk internal version 2-34 arbitration 4-1 Configuration Register map 2-97 contention with PPC 2-45 domain 4-9 FIFO 2-26 FIFO, as used with PCI Slave 2-22 http://www.motorola.com/computer/literature IN-5 I N D E X
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Page 273 and 274: SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276: Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
Page 283 and 284: ECC Codes ECC Codes When the Hawk r
Page 285 and 286: 4Hawk Programming Details Introduct
Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
Page 289 and 290: Exceptions Sources of Reset Soft Re
Page 291 and 292: Endian Issues Hawk Endian Issues Th
Page 293: Processor/Memory Domain MPIC’s In
Page 296 and 297: A Manufacturers’ Documents Manufa
Page 298 and 299: A Related Specifications Related Sp
Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 316 and 317: C Introduction The MVME2700 board,
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 325 and 326: devices, when Big-Endian 2-38 Maste
Page 327 and 328: om_a_rv and rom_b_rv encoding 3-55
Page 329: VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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