MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
5. Clear the derc and rwcb bits in the Data Control register.
6. Perform the desired testing related to the location/locations that
have had their check-bits altered.
7. Enable scrub writes by setting the swen bit if it was set before.
derc Setting derc to one alters SMC operation as follows:
1. During reads, data is presented to the PPC60x data bus uncorrected
from the SDRAM array.
2. During single-beat writes, data is written without correcting singlebit
errors that may occur on the read portion of the read-modifywrite.
Check-bits are generated for the data being written.
3. During single-beat writes, the write portion of the read-modifywrite
happens regardless of whether there is a multiple-bit error
during the read portion. No correction of data is attempted. Checkbits
are generated for the data being written.
4. During scrub cycles, if swen is set, a read-writes to SDRAM
happens with no attempt to correct data bits. Check-bits are
generated for the data being written.
derc is useful for initializing SDRAM after power-up and
for testing SDRAM, but it should be cleared during
normal system operation.
apien When apien is set, the logging of a PPC60x address parity
error causes the int bit to be set if it is not already. When
the int bit is set, the Hawk’s internal error interrupt is
asserted.
scien When scien is set, the rolling over of the
SBE COUNT register causes the int bit to be set if it is
not already. When the int bit is set, the Hawk’s internal
error interrupt is asserted.
dpien When dpien is set, the logging of a PPC60x data parity
error causes the int bit to be set if it is not already. When
the int bit is set, the Hawk’s internal error interrupt is
asserted.
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