MVME5100 Single Board Computer Programmer's Reference Guide

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3 System Memory Controller (SMC) DEVICE ADDR WORD ADDR DATA SDA M START S B A W C R K A C K A C K STOP BEGIN READ I 2 C STATUS REG CMPLT=1? N LOAD “$09” (START CONDITION) TO I 2 C CONTROL REG LOAD “DEVICE ADDR+WR BIT” TO I 2 C TRANSMITTER DATA REG LOAD “WORD ADDR” TO I 2 C TRANSMITTER DATA REG LOAD “DATA” TO I 2 C TRANSMITTER DATA REG Figure 3-5. Programming Sequence for I 2 C Byte Write 3-24 <strong>Computer</strong> Group Literature Center Web Site Y READ I 2 C STATUS REG CMPLT=ACKIN=1? Y READ I 2 C STATUS REG CMPLT=ACKIN=1? Y READ I 2 C STATUS REG CMPLT=ACKIN=1? LOAD “$05” (STOP CONDITION) TO I 2 C CONTROL REG LOAD “DUMMY DATA” TO I 2 C TRANSMITTER DATA REG Y READ I 2 C STATUS REG CMPLT=1? Y END N N N N * * * ACK from Slave Device (*): Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired
I 2 C Random Read Functional Description The I 2 C random read begins in the same manner as the I 2 C byte write. The first step in the programming sequence should be to test the i2_cmplt bit for the operation-complete status. The next step is to initiate a start sequence by first setting the i 2 _start and i 2 _enbl bits in the I 2 C Control Register and then writing the device address (bits 7-1) and write bit (bit 0=0) to the I 2 C Transmitter Data Register. The i 2 _cmplt bit will be automatically clear with the write cycle to the I 2 C Transmitter Data Register. The I 2 C Status Register must now be polled to test the i 2 _cmplt and i 2 _ackin bits. The i 2 _cmplt bit becomes set when the device address and write bit have been transmitted, and the i 2 _ackin bit provides status as to whether or not a slave device acknowledged the device address. With the successful transmission of the device address, the word address will be loaded into the I 2 C Transmitter Data Register to be transmitted to the slave device. Again, i 2 _cmplt and i 2 _ackin bits must be tested for proper response. At this point, the slave device is still in a write mode. Therefore, another start sequence must be sent to the slave to change the mode to read by first setting the i 2 _start and i 2 _enbl bits in the I 2 C Control Register and then writing the device address (bits 7-1) and read bit (bit 0=1) to the I 2 C Transmitter Data Register. After i 2 _cmplt and i 2 _ackin bits have been tested for proper response, the I 2 C master controller writes a dummy value (data=don’t care) to the I 2 C Transmitter Data Register.This causes the I 2 C master controller to initiate a read transmission from the slave device. Again, i2_cmplt bit must be tested for proper response. After the I 2 C master controller has received a byte of data (indicated by i 2 _datin=1 in the I 2 C Status Register), the system software may then read the data by polling the I 2 C Receiver Data Register. The I 2 C master controller does not acknowledge the read data for a single byte transmission on the I 2 C bus, but must complete the transmission by sending a stop sequence to the slave device. This can be accomplished by first setting the i 2 _stop and i 2 _enbl bits in the I 2 C Control Register and then writing a dummy data (data=don’t care) to the I 2 C Transmitter Data Register. The I 2 C Status Register must now be polled to test i 2 _cmplt bit for the operation-complete status. The stop sequence will relinquish the ASIC master’s possession of the I 2 C bus. Figure 3-6 shows the suggested software flow diagram for programming the I 2 C random read operation. http://www.motorola.com/computer/literature 3-25 3
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Page 171 and 172: The MPIC Memory Base Address Regist
Page 173 and 174: Registers INV Invalidate Enable. If
Page 175 and 176: Conceptual perspective from the PCI
Page 177 and 178: Registers CONFIG_DATA Register The
Page 179 and 180: 3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
Page 181 and 182: 3 1 3 0 2 9 2 8 2 7 Feature Reporti
Page 183 and 184: Registers M CASCADE MODE. Allows ca
Page 185 and 186: IPI Vector/Priority Registers Offse
Page 187 and 188: Timer Current Count Registers Offse
Page 189 and 190: Timer Vector/Priority Registers Off
Page 191 and 192: Registers MASK MASK. Setting this b
Page 193 and 194: Hawk Internal Error Interrupt Vecto
Page 195 and 196: Current Task Priority Registers Off
Page 197 and 198: 3System Memory Controller (SMC) Int
Page 199 and 200: PowerPC Side D[0:63] DP[0:7] Correc
Page 201 and 202: Figure 3-4. Hawk’s System Memory
Page 203 and 204: Page Holding SDRAM Speeds Functiona
Page 205 and 206: SDRAM Organization Functional Descr
Page 207 and 208: Cache Coherency Functional Descript
Page 209 and 210: Error Logging Functional Descriptio
Page 211 and 212: Functional Description When the wid
Page 213 and 214: Table 3-4. PPC60x to ROM/Flash (64
Page 215 and 216: ROM/Flash Speeds ACCESS TYPE Functi
Page 217 and 218: ACCESS TYPE Functional Description
Page 219: I 2 C Byte Write Functional Descrip
Page 223 and 224: I 2 C Current Address Read Function
Page 225 and 226: I 2 C Page Write Functional Descrip
Page 227 and 228: I 2 C Sequential Read Functional De
Page 229 and 230: SDA START DEVICE ADDR M S B BEGIN R
Page 231 and 232: Chip Configuration Programming Mode
Page 233 and 234: FEF80070 DPE_A FEF80078 DPE_DH FEF8
Page 235 and 236: Vendor/Device Register Address $FEF
Page 237 and 238: SDRAM Enable and Size Register (Blo
Page 239 and 240: SDRAM Base Address Register (Blocks
Page 241 and 242: drr value Programming Model us (64
Page 243 and 244: Normal View of Data (rwcb=0) Check-
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Page 247 and 248: Programming Model esbt esbt is set
Page 249 and 250: Scrub Address Register Programming
Page 251 and 252: Programming Model each half of the
Page 253 and 254: ROM B Base/Size Register Address Bi
Page 255 and 256: ROM Speed Attributes Registers Prog
Page 257 and 258: Data Parity Error Log Register Addr
Page 259 and 260: Data Parity Error Lower Data Regist
Page 261 and 262: I 2 C Status Register Programming M
Page 263 and 264: I 2 C Receiver Data Register Addres
Page 265 and 266: SDRAM Speed Attributes Register Pro
Page 267 and 268: Programming Model swr_dpl swr_dpl c
Page 269 and 270: 32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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