MVME5100 Single Board Computer Programmer's Reference Guide

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I N D E X SDRAM Enable and Size Register 3-41, 3-67 SDRAM Speed Attributes Register 3-69 Vendor/Device Register 3-39 SMC Data Parity Error Address Register 3-62 SMC Data Parity Error Log Register 3-61 SMC Data Parity Error Lower Data Register 3-63 SMC External Register Set 3-73 SMC Scrub Address Register 3-53 SMC tben Register 3-74 soft reset MPIC 4-5 software considerations 3-75 Hawk 3-75 Software Readable Header Register 1-29 sources of reset <strong>MVME5100</strong> 4-5 SPD 3-77 SPD JEDEC standard definition 1-12 Speculative PCI Request 2-47 spread I/O addressing as function of PHB 2-30 Spurious Vector Register 2-118 SRAM base address 3-35 status bit descriptions 3-38 Status Register 1-23, 1-24 strap pins configuration for the PC87308VUL 1-34 swen 3-52 syndrome codes ordered by bit in error 3-87 System Bus 1-8 System Controller Mode bit 1-24 System Memory Controller (SMC) 3-1 T TA as used with PPC Slave 2-7 Table 2-10 Table 2-2. 2-10 target initiated termination Index 2-24 TBEN Bit Register 1-27 tben Register SMC 3-74 Timer Basecount Registers 2-120 Timer Current Count Registers 2-119 Timer Destination Registers 2-122 Timer Frequency Register 2-118 Timer Vector/Priority Registers 2-121 timing (ROM/Flash access) 3-19 transaction(s) burst 2-8 compelled 2-7 instance of interrupt 2-8 ordering 2-48 PCI originated/PPC bound described 2-5 posted 2-7 PPC originated/PCI bound described 2-4 transactions PPC Slave limits 2-8 unable to retry 2-8 transfer types generated by PPC Master 2-14 PCI command code dependent 2-14 PPC60x bus 2-14 triple- (or greater) bit error 3-12 Tundra Universe Controller 1-2 U Universe ASIC 1-17 Universe chip problems after a PCI reset 4-5 Universe VMEbus interface ASIC 1-8, 1-15 User configuration Data 1-13 V Vendor ID/ Device ID Registers 2-98 Vendor ID/Device ID Registers 2-70 Vendor Identification Register 2-116 Vendor/Device Register SMC 3-39 Vital Product Data 1-10, 1-13 Vital Product Data (VPD) B-1 IN-10 <strong>Computer</strong> Group Literature Center Web Site
VME Processor Module MVME510x 1-1 VMEbus 1-2 memory map 1-8 memory maps 1-8 VPD B-1 VPD - FLASH Memory Configuration Data B-9 VPD - L2 Cache Configuration Data B-10 VPD - Product Configuration Options B-7 VPD - Revision Data B-12 VPD definitions B-4 VPD SROM 1-10 VPD/SPD explained 1-14 W Watchdog Timer registers 2-43 watchdog timers as part of PHB 2-42 WDTxCNTL register 2-43 WDTxCNTL Registers 2-92 WDTxSTAT Registers 2-96 write posting as part of PHB tuning 2-11 writing to the control registers 3-75 Z Z8536 CIO port pins assignment 1-36 http://www.motorola.com/computer/literature IN-11 I N D E X
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
Page 283 and 284: ECC Codes ECC Codes When the Hawk r
Page 285 and 286: 4Hawk Programming Details Introduct
Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
Page 289 and 290: Exceptions Sources of Reset Soft Re
Page 291 and 292: Endian Issues Hawk Endian Issues Th
Page 293: Processor/Memory Domain MPIC’s In
Page 296 and 297: A Manufacturers’ Documents Manufa
Page 298 and 299: A Related Specifications Related Sp
Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 316 and 317: C Introduction The MVME2700 board,
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323 and 324: L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 325 and 326: devices, when Big-Endian 2-38 Maste
Page 327: om_a_rv and rom_b_rv encoding 3-55
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MVME5100 Single Board Computer Programmer's Reference Guide

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