MVME5100 Single Board Computer Programmer's Reference Guide

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viii The Universe ASIC .......................................................................................... 1-17 PCI Configuration Space.................................................................................. 1-19 Hawk External Register Bus Address Assignments......................................... 1-21 <strong>MVME5100</strong> Hawk External Register Bus Summary ............................... 1-21 Dual TL16C550 UARTs................................................................................... 1-23 Status Register.................................................................................................. 1-24 MODFAIL Bit Register.................................................................................... 1-25 MODRST Bit Register ..................................................................................... 1-26 TBEN Bit Register ........................................................................................... 1-27 NVRAM/RTC & Watchdog Timer................................................................... 1-28 Software Readable Header/Switch Register (S1)............................................. 1-29 Geographical Address Register (VME board) ................................................. 1-30 Extended Features Register 1........................................................................... 1-31 <strong>Board</strong> Last Reset Register ................................................................................ 1-32 Extended Features Register 2........................................................................... 1-33 IPMC7xx ISA Bus Resources ................................................................................. 1-34 W83C554 PIB Registers .................................................................................. 1-34 PC87308VUL Super I/O (ISASIO) Strapping ................................................. 1-34 Z85230 ESCC and Z8536 CIO Registers and Port Pins .................................. 1-35 Z8536/Z85230 Registers........................................................................... 1-35 Z8536 CIO Port Pins................................................................................. 1-36 ISA DMA Channels ......................................................................................... 1-39 CHAPTER 2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller Introduction ............................................................................................................... 2-1 Overview ............................................................................................................ 2-1 Features .............................................................................................................. 2-1 Block Diagram........................................................................................................... 2-3 Functional Description .............................................................................................. 2-4 Architectural Overview ...................................................................................... 2-4 PPC Bus Interface .............................................................................................. 2-5 PPC Address Mapping ................................................................................ 2-6 PPC Slave.................................................................................................... 2-7 PPC FIFO .................................................................................................... 2-9 PPC Master................................................................................................ 2-10 PPC Arbiter ............................................................................................... 2-15 PPC Parity ................................................................................................. 2-17 PPC Bus Timer.......................................................................................... 2-18 PCI Bus Interface ............................................................................................. 2-19 PCI Address Mapping ............................................................................... 2-19
PCI Slave ...................................................................................................2-22 PCI FIFO ...................................................................................................2-26 PCI Master.................................................................................................2-26 Generating PCI Cycles ..............................................................................2-29 PCI Arbiter ................................................................................................2-34 Endian Conversion............................................................................................2-38 When PPC Devices are Big-Endian ..........................................................2-38 When PPC Devices are Little Endian........................................................2-39 PHB Registers............................................................................................2-40 Error Handling ..................................................................................................2-41 Watchdog Timers ..............................................................................................2-42 PCI/PPC Contention Handling .........................................................................2-45 Transaction Ordering ........................................................................................2-48 PHB Hardware Configuration ..........................................................................2-49 Multi-Processor Interrupt Controller (MPIC)..........................................................2-51 MPIC Features: .................................................................................................2-51 Architecture ......................................................................................................2-51 External Interrupt Interface...............................................................................2-52 CSR’s Readability.............................................................................................2-53 Interrupt Source Priority ...................................................................................2-53 Processor’s Current Task Priority .....................................................................2-54 Nesting of Interrupt Events...............................................................................2-54 Spurious Vector Generation..............................................................................2-54 Interprocessor Interrupts (IPI) ..........................................................................2-55 8259 Compatibility ...........................................................................................2-55 Hawk Internal Errror Interrupt..........................................................................2-55 Timers ...............................................................................................................2-56 Interrupt Delivery Modes..................................................................................2-56 Block Diagram Description ..............................................................................2-57 Program Visible Registers.........................................................................2-59 Interrupt Pending Register (IPR)...............................................................2-59 Interrupt Selector (IS)................................................................................2-59 Interrupt Request Register (IRR)...............................................................2-60 In-Service Register (ISR) ..........................................................................2-60 Interrupt Router .........................................................................................2-60 Programming Notes ..........................................................................................2-62 External Interrupt Service..........................................................................2-62 Reset State .................................................................................................2-63 Operation ..........................................................................................................2-64 Interprocessor Interrupts............................................................................2-64 Dynamically Changing I/O Interrupt Configuration .................................2-64 EOI Register ..............................................................................................2-65 ix
Page 1 and 2: MVME5100 Single Board Computer Prog
Page 3 and 4: Safety Summary The following genera
Page 5 and 6: CE Notice (European Community) Moto
Page 7: Contents About This Manual Summary
Page 11 and 12: Spurious Vector Register...........
Page 13 and 14: Address Parity Error Log Register .
Page 15: List of Figures Figure 1-1. MVME510
Page 18 and 19: xviii Table 2-13. Address Modificat
Page 21 and 22: About This Manual The MVME5100 Sing
Page 23 and 24: Part Number Description MVME761-011
Page 25 and 26: 8259 Interrupts, and a description
Page 27: In this manual, assertion and negat
Page 30 and 31: 1 Product Data and Memory Maps Main
Page 32 and 33: 1 Product Data and Memory Maps Memo
Page 34 and 35: 1 Product Data and Memory Maps Tabl
Page 36 and 37: 1 Product Data and Memory Maps PCI
Page 38 and 39: 1 Product Data and Memory Maps L2 C
Page 40 and 41: 1 Product Data and Memory Maps conn
Page 42 and 43: 1 Product Data and Memory Maps to i
Page 44 and 45: 1 Product Data and Memory Maps Requ
Page 46 and 47: 1 Product Data and Memory Maps PROC
Page 48 and 49: 1 Product Data and Memory Maps The
Page 50 and 51: 1 Product Data and Memory Maps Tabl
Page 52 and 53: 1 Product Data and Memory Maps Stat
Page 54 and 55: 1 Product Data and Memory Maps MODR
Page 56 and 57: 1 Product Data and Memory Maps NVRA
Page 58 and 59:
1 Product Data and Memory Maps Geog
Page 60 and 61:
1 Product Data and Memory Maps Boar
Page 62 and 63:
1 Product Data and Memory Maps IPMC
Page 64 and 65:
1 Product Data and Memory Maps Z853
Page 66 and 67:
1 Product Data and Memory Maps IDRE
Page 69 and 70:
2Hawk PCI Host Bridge & Multi- Proc
Page 71 and 72:
Block Diagram PCI Bus MPIC Interfac
Page 73 and 74:
PPC Bus Interface Functional Descri
Page 75 and 76:
PPC Slave Functional Description Ea
Page 77 and 78:
PPC FIFO PPC Transfer Type Transfer
Page 79 and 80:
Functional Description Table 2-2. P
Page 81 and 82:
Table 2-4. PPC Master Read Ahead Op
Page 83 and 84:
PPC Arbiter Pin Name Functional Des
Page 85 and 86:
PPC Parity Functional Description T
Page 87 and 88:
PCI Bus Interface PCI Address Mappi
Page 89 and 90:
Functional Description Each map dec
Page 91 and 92:
Command Types: Functional Descripti
Page 93 and 94:
Fast Back-to-Back Transactions Func
Page 95 and 96:
Functional Description It should be
Page 97 and 98:
Functional Description The PCI Mast
Page 99 and 100:
. Figure 2-6. PCI Spread I/O Addres
Page 101 and 102:
Functional Description The device t
Page 103 and 104:
Functional Description The Hawk’s
Page 105 and 106:
Functional Description Notes 1. “
Page 107 and 108:
. DH07-00 DH15-08 DH23-16 DH31-24 F
Page 109 and 110:
Error Handling Functional Descripti
Page 111 and 112:
Functional Description When not bei
Page 113 and 114:
Functional Description PPC1-Bug>md
Page 115 and 116:
Functional Description From the per
Page 117 and 118:
Functional Description ❏ Write po
Page 119 and 120:
Multi-Processor Interrupt Controlle
Page 121 and 122:
CSR’s Readability Multi-Processor
Page 123 and 124:
Interprocessor Interrupts (IPI) 825
Page 125 and 126:
Page 127 and 128:
Program Visible Registers Multi-Pro
Page 129 and 130:
Page 131 and 132:
Reset State Multi-Processor Interru
Page 133 and 134:
EOI Register Multi-Processor Interr
Page 135 and 136:
Registers Registers This section pr
Page 137 and 138:
Bit ---> Table 2-16. PPC Register M
Page 139 and 140:
General Control-Status/Feature Regi
Page 141 and 142:
PPC Arbiter/PCI Arbiter Control Reg
Page 143 and 144:
Registers PRKx Parking. This field
Page 145 and 146:
Hardware Control-Status/Prescaler A
Page 147 and 148:
PPC Error Test/Error Enable Registe
Page 149 and 150:
Registers XBTOI PPC Address Bus Tim
Page 151 and 152:
Registers PPER PCI Parity Error. Th
Page 153 and 154:
PPC Error Attribute Register Regist
Page 155 and 156:
PCI Interrupt Acknowledge Register
Page 157 and 158:
PPC Slave Offset/Attribute (0, 1 an
Page 159 and 160:
The fields within XSADD3 are define
Page 161 and 162:
Registers KEY Key. This field is us
Page 163 and 164:
PPC6-Bug>mw feff0068 aa88;h Effecti
Page 165 and 166:
PCI Registers 3 1 3 0 2 9 2 8 2 7 2
Page 167 and 168:
PCI Command/ Status Registers Regis
Page 169 and 170:
Revision ID/ Class Code Registers O
Page 171 and 172:
The MPIC Memory Base Address Regist
Page 173 and 174:
Registers INV Invalidate Enable. If
Page 175 and 176:
Conceptual perspective from the PCI
Page 177 and 178:
Registers CONFIG_DATA Register The
Page 179 and 180:
3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
Page 181 and 182:
3 1 3 0 2 9 2 8 2 7 Feature Reporti
Page 183 and 184:
Registers M CASCADE MODE. Allows ca
Page 185 and 186:
IPI Vector/Priority Registers Offse
Page 187 and 188:
Timer Current Count Registers Offse
Page 189 and 190:
Timer Vector/Priority Registers Off
Page 191 and 192:
Registers MASK MASK. Setting this b
Page 193 and 194:
Hawk Internal Error Interrupt Vecto
Page 195 and 196:
Current Task Priority Registers Off
Page 197 and 198:
3System Memory Controller (SMC) Int
Page 199 and 200:
PowerPC Side D[0:63] DP[0:7] Correc
Page 201 and 202:
Figure 3-4. Hawk’s System Memory
Page 203 and 204:
Page Holding SDRAM Speeds Functiona
Page 205 and 206:
SDRAM Organization Functional Descr
Page 207 and 208:
Cache Coherency Functional Descript
Page 209 and 210:
Error Logging Functional Descriptio
Page 211 and 212:
Functional Description When the wid
Page 213 and 214:
Table 3-4. PPC60x to ROM/Flash (64
Page 215 and 216:
ROM/Flash Speeds ACCESS TYPE Functi
Page 217 and 218:
ACCESS TYPE Functional Description
Page 219 and 220:
I 2 C Byte Write Functional Descrip
Page 221 and 222:
I 2 C Random Read Functional Descri
Page 223 and 224:
I 2 C Current Address Read Function
Page 225 and 226:
I 2 C Page Write Functional Descrip
Page 227 and 228:
I 2 C Sequential Read Functional De
Page 229 and 230:
SDA START DEVICE ADDR M S B BEGIN R
Page 231 and 232:
Chip Configuration Programming Mode
Page 233 and 234:
FEF80070 DPE_A FEF80078 DPE_DH FEF8
Page 235 and 236:
Vendor/Device Register Address $FEF
Page 237 and 238:
SDRAM Enable and Size Register (Blo
Page 239 and 240:
SDRAM Base Address Register (Blocks
Page 241 and 242:
drr value Programming Model us (64
Page 243 and 244:
Normal View of Data (rwcb=0) Check-
Page 245 and 246:
! Caution Programming Model sien Wh
Page 247 and 248:
Programming Model esbt esbt is set
Page 249 and 250:
Scrub Address Register Programming
Page 251 and 252:
Programming Model each half of the
Page 253 and 254:
ROM B Base/Size Register Address Bi
Page 255 and 256:
ROM Speed Attributes Registers Prog
Page 257 and 258:
Data Parity Error Log Register Addr
Page 259 and 260:
Data Parity Error Lower Data Regist
Page 261 and 262:
I 2 C Status Register Programming M
Page 263 and 264:
I 2 C Receiver Data Register Addres
Page 265 and 266:
SDRAM Speed Attributes Register Pro
Page 267 and 268:
Programming Model swr_dpl swr_dpl c
Page 269 and 270:
32-Bit Counter Address $FEF80100 Bi
Page 271 and 272:
Software Considerations When the tb
Page 273 and 274:
SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276:
Software Considerations c. If a CAS
Page 277 and 278:
Software Considerations Notes 1. Us
Page 279 and 280:
Software Considerations 8. Now that
Page 281 and 282:
2. For each of the Blocks A through
Page 283 and 284:
ECC Codes ECC Codes When the Hawk r
Page 285 and 286:
4Hawk Programming Details Introduct
Page 287 and 288:
8259 Interrupts PRI PSIO IRQ Input
Page 289 and 290:
Exceptions Sources of Reset Soft Re
Page 291 and 292:
Endian Issues Hawk Endian Issues Th
Page 293:
Processor/Memory Domain MPIC’s In
Page 296 and 297:
A Manufacturers’ Documents Manufa
Page 298 and 299:
A Related Specifications Related Sp
Page 300 and 301:
B MVME5100 VPD Reference Informatio
Page 302 and 303:
Page 304 and 305:
Page 306 and 307:
Page 308 and 309:
Page 310 and 311:
Page 312 and 313:
Page 314 and 315:
Page 316 and 317:
C Introduction The MVME2700 board,
Page 319 and 320:
Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322:
E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323 and 324:
L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 325 and 326:
devices, when Big-Endian 2-38 Maste
Page 327 and 328:
om_a_rv and rom_b_rv encoding 3-55
Page 329:
VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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