MVME5100 Single Board Computer Programmer's Reference Guide

PPC Error Test/Error Enable Register
Registers
The Error Test Register (ETEST) provides you with a way to send certain
types of errors to test the PHB error capture and status circuitry. The bits
within the ETEST are defined as follows:
0
Address
Bit
$FEFF0020
Name ETEST EENAB
Operation
Reset 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DPE0
DPE1
DPE2
DPE3
DPE4
DPE5
DPE6
DPE7
APE0
APE1
APE2
APE3
DFLT
XBTOM
XDPEM
PPERM
PSERM
PSMAM
PRTAM
XBTOII
XDPEI
PPERI
PSERI
PSMAI
PRTAI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DPEx Data Parity Error Enable. These bits are used for test
reasons to purposely inject data parity errors whenever the
PHB is sourcing PPC data. A data parity error will be
created on the corresponding PPC data parity bus if a bit
is set. For example, setting DPE0 will cause DP0 to be
generated incorrectly. If the bit is cleared, the PHB will
generate correct data parity.
APEx Address Parity Error Enable. These bits are used for
test reasons to purposely inject address parity errors
whenever the PHB is acting as a PPC bus master. An
address parity error will be created on the corresponding
PPC address parity bus if a bit is set. For example, setting
APE0 will cause AP0 to be generated incorrectly. If the bit
is cleared, the PHB will generate correct address parity.
The Error Enable Register (EENAB) controls how the PHB is to respond
to the detection of various errors. In particular, each error type can
uniquely be programmed to generate a machine check, generate an
interrupt, generate both, or generate neither. The bits within the ETEST are
defined as follows:
http://www.motorola.com/computer/literature 2-79
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