MVME5100 Single Board Computer Programmer's Reference Guide

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I N D E X functions of Master 2-26 Interface features 2-1 Master Command Codes 2-27 Master explained 2-4 purpose of interface 2-19 registers 2-97 slave 2-22 Slave disconnect scenarios 2-24 slave response command types 2-23 Slave with PCI Master 2-26 speculative requests 2-47 spread I/O address translation 2-31 to MPC address decoding 2-20 to MPC address translation 2-21 write posting 2-26 PCI / VME Memory Map 1-7 PCI Arbitration Assignments for Hawk ASI 1-15 PCI bus 1-8 PCI Command/ Status Registers 2-99 PCI Configuration Space 1-19 PCI Expansion Connector 1-2 PCI expansion slot arbiter 1-15 PCI Host Bridge 1-2 PCI Interrupt Acknowledge Register 2-87 PCI Local Bus 1-15 PCI Slave Address (0,1,2 and 3) Registers 2-103 PCI Slave Attribute/ Offset (0,1,2 and 3) Registers 2-104 PCI/PMC/Expansion 1-2 PCIX slot 1-17 performance SMC 3-6 Peripheral Support 1-2 PHB 2-1 address mapping 2-6 Configuration registers, mapped in PCI Configuration space 2-19 configuration type 2-31 contention handling explained 2-45 Index endian conversion 2-38 error types described 2-41 Hawk 1-4 PPC register map 2-68 Registers described 2-40 retuning write thresholds 2-11 spread I/O addressing 2-30 watchdog timers 2-42 PHB-Detected Errors Destination Register 2-126 PHB-Detected Errors Vector/Priority Register 2-125 PIB DMA channel assignments 1-39 pipelining removing 2-7 Planar PCI Device Identification 1-20 PMC slot 1 arbiter 1-15 slot 2 arbiter 1-15 PMC mode 1-11 PMC/PCI Expansion Slots 1-17 PowerPC 60x address to ROM/Flash address mapping with 2, 32-bit or 1, 64-bit 3-17 PowerPC 60x bus to ROM/Flash access timing using 32/64-bit devices 3-19 PowerPC 60x bus to ROM/Flash access timing using 8-bit devices 3-20 PowerPC 60x to 16bit wide ROM/Flash address mapping 3-16 PowerPlus II architecture 1-1 Power-Up Reset status bit 3-45 PPC address mapping 2-6 Bus Address Space 2-20 bus arbiter 2-15 Bus connections 2-5 Bus features 2-1 bus interface explained 2-5 bus timer 2-18 contention with PCI 2-45 devices, as little endian 2-39 IN-6 <strong>Computer</strong> Group Literature Center Web Site
devices, when Big-Endian 2-38 Master 2-10 Master, Bug Hog 2-14 Master, doing prefetched reads 2-13 Master, read ahead mode 2-12 parity 2-17 register map 2-68 registers 2-68 slave’s role 2-7 to PCI address translation 2-7 write posting 2-9 PPC Arbiter debug functions 2-16 parking modes 2-16 prioritization schemes 2-16 PPC Arbiter Control Register 2-73 PPC Error Address Register 2-84 PPC Error Attribute Register - EATTR 2-85 PPC Error Enable Register 2-79 PPC Error Status Register 2-82 PPC Slave Address (0,1 and 2) Registers 2-88 PPC Slave Address (3) Register 2-89 PPC Slave Address Register 2-90 PPC Slave Offset/Attribute (0,1 and 2) Registers 2-91 PPC60x Bus Interface SMC 3-9 PPC60x Data Parity 3-10 Prescaler Adjust Register 2-77 priority schemes described (PCI arbiter) 2-35 PRK as used in arbitration parking 2-37 Processor Init Register 2-116 processor internal clock frequenc 1-9 Processor Memory Map 1-4 Processor PLL Configuration 1-9 Processor Type Identification 1-9 Processor Version Register (PVR) 1-9 processor/memory domain MPC750 4-9 Processors 1-9 programmable DMA Controller 1-2 Programmable Lock Resolution 2-46 programming details 1-1, 4-1 programming information added resources xxi programming ROM/Flash devices 3-75 PVR value 1-9 R RAM A BASE 3-43, 3-68 RAM B BASE 3-43, 3-68 RAM C BASE 3-43, 3-68 RAM D BASE 3-43, 3-66, 3-67, 3-68 read ahead mode in PPC Master 2-12 Read/Write Checkbits control bit 3-46 Read/Write to ROM/Flash 3-56 refdis 3-46 refresh/scrub 3-34 SMC 3-34 Refresh/Scrub Address Register SMC 3-53 register Status 1-24 register bit descriptions SMC 3-38 register map 2-68 PCI 2-97 PPC 2-68 register summary 3-36 registers CLK Frequency 3-44 CONFIG_ADDRESS 2-106 CONFIG_DATA 2-109 Current Task Priority 2-127 End-of-Interrupt 2-128 External Source Destination 2-124 External Source Vector/Priority 2-122 Feature Reporting 2-113 General Purpose 2-96 Global Configuration 2-114 Hardware Control-Status Register 2-77 http://www.motorola.com/computer/literature IN-7 I N D E X
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
Page 273 and 274: SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276: Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
Page 283 and 284: ECC Codes ECC Codes When the Hawk r
Page 285 and 286: 4Hawk Programming Details Introduct
Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
Page 289 and 290: Exceptions Sources of Reset Soft Re
Page 291 and 292: Endian Issues Hawk Endian Issues Th
Page 293: Processor/Memory Domain MPIC’s In
Page 296 and 297: A Manufacturers’ Documents Manufa
Page 298 and 299: A Related Specifications Related Sp
Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 316 and 317: C Introduction The MVME2700 board,
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323: L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 327 and 328: om_a_rv and rom_b_rv encoding 3-55
Page 329: VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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