MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
Block Diagrams
PPC60x Bus
❏ ROM/Flash Interface
– Two blocks with each block being 16 or 64 bits wide.
– Programmable access time on a per-block basis.
❏ I 2 C master interface.
❏ External status/control register support
Figure 3-1 depicts a Hawk as it would be connected with SDRAMs in a
system. Figure 3-2 shows the SMC’s internal data paths. Figure 3-3 shows
the overall SDRAM connections. Figure 3-4 shows a block diagram of the
SMC portion of the Hawk ASIC.
PowerPC
Data (64 Bits)
PowerPC
Data Parity (8 Bits)
PowerPC
Address &Control
PowerPC
Address Parity (4 bits)
HAWK
SDRAM
Data (64 Bits)
SDRAM
Address & Control
SDRAM
Check Bits (8 Bits)
Figure 3-1. Hawk Used with Synchronous DRAM in a System
Synch
DRAM
Data
Check
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