MVME5100 Single Board Computer Programmer's Reference Guide

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2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller PPC Registers Bit ---> The PPC register map of the PHB is shown in Table 2-16. Table 2-16. PPC Register Map for PHB 0 1 2 3 4 5 6 7 8 9 1 0 $FEFF0000 VENID DEVID $FEFF0004 REVID $FEFF0008 GCSR $FEFF000C XARB PARB 1 1 $FEFF0010 XPAD $FEFF0014 $FEFF0018 $FEFF001C $FEFF0020 ETEST EENAB 1 2 $FEFF0024 ESTAT $FEFF0028 EADDR $FEFF002C EATTR $FEFF0030 PIACK $FEFF0034 $FEFF0038 $FEFF003C $FEFF0040 XSADD0 $FEFF0044 XSOFF0 XSATT0 1 3 2-68 <strong>Computer</strong> Group Literature Center Web Site 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1
Bit ---> Table 2-16. PPC Register Map for PHB (Continued) 0 1 2 3 4 5 6 7 8 9 $FEFF0048 XSADD1 $FEFF004C XSOFF1 XSATT1 $FEFF0050 XSADD2 $FEFF0054 XSOFF2 XSATT2 $FEFF0058 XSADD3 $FEFF005C XSOFF3 XSATT3 $FEFF0060 WDT1CNTL $FEFF0064 WDT1STAT $FFEF0068 WDT2CNTL $FEFF006C WDT2STAT $FEFF0070 GPREG0(Upper) $FEFF0074 GPREG0(Lower) $FEFF0078 GPREG1(Upper) $FEFF007C GPREG1(Lower) 1 0 1 1 1 2 1 3 Registers http://www.motorola.com/computer/literature 2-69 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 2
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
Page 85 and 86: PPC Parity Functional Description T
Page 87 and 88: PCI Bus Interface PCI Address Mappi
Page 89 and 90: Functional Description Each map dec
Page 91 and 92: Command Types: Functional Descripti
Page 93 and 94: Fast Back-to-Back Transactions Func
Page 95 and 96: Functional Description It should be
Page 97 and 98: Functional Description The PCI Mast
Page 99 and 100: . Figure 2-6. PCI Spread I/O Addres
Page 101 and 102: Functional Description The device t
Page 103 and 104: Functional Description The Hawk’s
Page 105 and 106: Functional Description Notes 1. “
Page 107 and 108: . DH07-00 DH15-08 DH23-16 DH31-24 F
Page 109 and 110: Error Handling Functional Descripti
Page 111 and 112: Functional Description When not bei
Page 113 and 114: Functional Description PPC1-Bug>md
Page 115 and 116: Functional Description From the per
Page 117 and 118: Functional Description ❏ Write po
Page 119 and 120: Multi-Processor Interrupt Controlle
Page 121 and 122: CSR’s Readability Multi-Processor
Page 123 and 124: Interprocessor Interrupts (IPI) 825
Page 127 and 128: Program Visible Registers Multi-Pro
Page 131 and 132: Reset State Multi-Processor Interru
Page 133 and 134: EOI Register Multi-Processor Interr
Page 135: Registers Registers This section pr
Page 139 and 140: General Control-Status/Feature Regi
Page 141 and 142: PPC Arbiter/PCI Arbiter Control Reg
Page 143 and 144: Registers PRKx Parking. This field
Page 145 and 146: Hardware Control-Status/Prescaler A
Page 147 and 148: PPC Error Test/Error Enable Registe
Page 149 and 150: Registers XBTOI PPC Address Bus Tim
Page 151 and 152: Registers PPER PCI Parity Error. Th
Page 153 and 154: PPC Error Attribute Register Regist
Page 155 and 156: PCI Interrupt Acknowledge Register
Page 157 and 158: PPC Slave Offset/Attribute (0, 1 an
Page 159 and 160: The fields within XSADD3 are define
Page 161 and 162: Registers KEY Key. This field is us
Page 163 and 164: PPC6-Bug>mw feff0068 aa88;h Effecti
Page 165 and 166: PCI Registers 3 1 3 0 2 9 2 8 2 7 2
Page 167 and 168: PCI Command/ Status Registers Regis
Page 169 and 170: Revision ID/ Class Code Registers O
Page 171 and 172: The MPIC Memory Base Address Regist
Page 173 and 174: Registers INV Invalidate Enable. If
Page 175 and 176: Conceptual perspective from the PCI
Page 177 and 178: Registers CONFIG_DATA Register The
Page 179 and 180: 3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
Page 181 and 182: 3 1 3 0 2 9 2 8 2 7 Feature Reporti
Page 183 and 184: Registers M CASCADE MODE. Allows ca
Page 185 and 186: IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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