MVME5100 Single Board Computer Programmer's Reference Guide

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B MVME5100 VPD Reference Information VPD Definitions - L2 Cache Configuration Data Byte Offset Field Size (Bytes) The L2 cache configuration data packet consists of byte fields that show the size, organization, and type of the L2 cache memory array. Note: The PPMCBASE does not contain L2 Cache . The following table(s) further describe the L2 cache memory configuration VPD data packet. Table B-4. L2 Cache Configuration Data Field Mnemonic Field Description 00 2 L2C_MID Manufacturer’s Identifier (FFFF = Undefined/Not-Applicable) 02 2 L2C_DID Manufacturer’s Device Identifier (FFFF = Undefined/Not-Applicable) 04 1 L2C_DDW Device Data Width (e.g., 8-bits, 16-bits, 32bits, 64-bits, 128-bits) 05 1 L2C_NOD Number of Devices Present 06 1 L2C_NOC Number of Columns (Interleaves) 07 1 L2C_CW Column Width in Bits This will always be a multiple of the device’s data width. 08 1 L2C_TYPE L2 Cache Type: 00 - Arthur Backside 01 - External 02 - In-Line 09 1 L2C_ASSOCIATE Associative Microprocessor Number (If Applicable) 0A 1 L2C_OPERATIONMODE Operation Mode: 00 - Either Write-Through or Write-Back (S/W Configurable) 01 - Either Write-Through or Write-Back (H/W Configurable) 02 - Write-Through Only 03 - Write-Back Only B-10 Computer Group Literature Center Web Site
Byte Offset Vital Product Data (VPD) Introduction Table B-4. L2 Cache Configuration Data (Continued) Field Size (Bytes) Field Mnemonic Field Description 0B 1 L2C_ERROR_DETECT Error Detection Type: 00 - None 01 - Parity 02 - ECC 0C 1 L2C_SIZE L2 Cache Size (Should agree with the physical organization above): 00 - 256K 01 - 512K 02 - 1M 03 - 2M 04 - 4M 0D 1 L2C_TYPE_BACKSIDE L2 Cache Type (Backside Configurations): 00 - Late Write Sync, 1nS Hold, Differential Clock, Parity 01 - Pipelined Sync Burst, 0.5nS Hold, No Differentia Clock, Parity 02 - Late Write Sync, 1nS Hold, Differential Clock, No Parity 03 - Pipelined Sync Burst, 0.5nS Hold, No Differential Clock, No Parity 0E 1 L2C_RATIO_BACKSIDE L2 Cache Core to Cache Ration (Backside Configurations): 00 - Disabled 01 - 1:1 (1) 02 - 3:2 (1.5) 03 - 2:1 (2) 04 - 5:2 (2.5) 05 - 3:1 (3) A product may contain multiple L2 cache configuration packets. This product, the PPMCBASE, does not contain a L2 Cache device. http://www.motorola.com/computer/literature B-11 B
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Page 267 and 268: Programming Model swr_dpl swr_dpl c
Page 269 and 270: 32-Bit Counter Address $FEF80100 Bi
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Page 273 and 274: SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276: Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
Page 283 and 284: ECC Codes ECC Codes When the Hawk r
Page 285 and 286: 4Hawk Programming Details Introduct
Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
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Page 291 and 292: Endian Issues Hawk Endian Issues Th
Page 293: Processor/Memory Domain MPIC’s In
Page 296 and 297: A Manufacturers’ Documents Manufa
Page 298 and 299: A Related Specifications Related Sp
Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 316 and 317: C Introduction The MVME2700 board,
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323 and 324: L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 325 and 326: devices, when Big-Endian 2-38 Maste
Page 327 and 328: om_a_rv and rom_b_rv encoding 3-55
Page 329: VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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