MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
:
Generating PCI Memory and I/O Cycles
Each programmable slave may be configured to generate PCI I/O or
memory accesses through the MEM and IOM fields in its XSATTx
register as shown below.
MEM IOM PCI Cycle Type
1 x Memory
0 0 Contiguous I/O
0 1 Spread I/O
If the MEM bit is set, the PHB performs Memory addressing on the PCI
bus. The PHB takes the PPC bus address, applies the offset specified in the
XSOFFx register, and maps the result directly to the PCI bus.
The IBM CHRP specification describes two approaches for handling PCI
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the IOM bit is used to select between these two modes whenever
a PCI I/O cycle is to be performed.
The PHB performs contiguous I/O addressing when the MEM bit is clear
and the IOM bit is clear. The PHB takes the PPC address, apply the offset
specified in the XSOFFx register, and map the result directly to PCI.
The PHB performs spread I/O addressing when the MEM bit is clear and
the IOM bit is set. The PHB takes the PPC address, applies the offset
specified in the MSOFFx register, and maps the result to PCI as shown in
Figure 2-6.
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