MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
End-of-Interrupt Registers
Offset Processor 0 $200B0
Processor 1 $210B0
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
EOI END OF INTERRUPT. There is one EOI register per
processor. EOI Code values other than 0 are currently
undefined. Data values written to this register are ignored;
zero is assumed. Writing to this register signals the end of
processing for the highest priority interrupt currently in
service by the associated processor. The write operation
will update the In-Service register by retiring the highest
priority interrupt. Reading this register returns zeros.
2-128 Computer Group Literature Center Web Site
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name EOI
Operation R R R R W
Reset $00 $00 $00 $0 $0