MVME5100 Single Board Computer Programmer's Reference Guide

I
N
D
E
X
Global Configuration Register 2-114
H
Hardware Control-Status Register 2-77
Hawk
address parity 3-10
as MPU/PCI bus bridge controller ASIC
1-15
block diagram 2-3
configuration options 3-35
data parity 3-10
ECC Codes 3-87
Error Correction Codes 3-87
error notification and handling 4-6
I2C Byte Write 3-23
I2C Current Address Read 3-27
I2C Page Write 3-29
I2C Random Read 3-25
I2C Sequential Read 3-31
MPIC control registers 2-22
MPIC interrupt assignments 4-1
MPIC interrupts 4-1
MPIC register map 2-110
PCI Host Bridge & Multi-Processor Interrupt
Controller chip 2-1
programming details 4-1
programming ROM/Flash devices 3-75
SMC 3-1
software considerations 3-75
System Memory Controller block diagram
3-3
used with DRAM in a system 3-2
writing to the control registers 3-75
Hawk ASIC 1-12
Hawk External Register Bus Summar 1-21
Hawk I2C interface and configuration information
1-13
Hawk PCI Host Bridge 1-2
Hawk System Memory Controller 1-2
Hawk’s DEVSEL_ pin
as criteria for PHB config. mapping 2-19
Hawk’s I2C bus 3-77
Index
Hawk’s PCI arbiter
priority schemes 2-35
Hawk’s SMC
overview 3-1
HCSR
Hardware Control-Status Register 2-77
Header/Type Register 2-101
I
I/O Base Register
MPIC 2-102
I2C
Byte Write, Hawk 3-23
Current Address Read, Hawk 3-27
EEPROMs 3-77
Page Write, Hawk 3-29
Random Read, Hawk 3-25
Sequential Read, Hawk 3-31
I2C Receiver Data Register 3-67
IDSEL Mapping for PCI Devices 1-19
initializing
SDRAM-related control registers 3-76
Inter-Integrated Circuit 1-13
Internal Clock Frequency 1-1
interpretation of MID3-MID0 1-37
Interprocessor Interrupt Dispatch Registers
2-126
Interrupt Acknowledge Registers 2-127
Interrupt Controller 1-2
features 2-2
Interrupt Enable control bits 3-48
interrupts
8259 4-3
Hawk MPIC 4-1
introduction 1-1
Hawk PHB/MPIC 2-1
PHB/MPIC 2-1
programming details for Hawk 4-1
SMC 3-1
IPI Vector/Priority Registers 2-117
IN-4 Computer Group Literature Center Web Site