MVME5100 Single Board Computer Programmer's Reference Guide

PPC Arbiter/PCI Arbiter Control Registers
Registers
The PPC Arbiter Register (XARB) provides control and status for the PPC
Arbiter. Refer to the section titled PPC Arbiter for more information. The
bits within the XARB register are defined as follows:
Address $FEFF000C
Bit
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
Name XARB PARB
FSW0
FSW1
FSW0
FBW1
FSR0
FSR1
FBR0
FBR1
Operation RW R
Reset 0
PRK0
PRK1
PRI
POL
HIER0
HIER1
HIER2
PRK0
PRK1
PRK2
PRK3
PRI0
PRI1
ENA
FBRx Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
FSRx Flatten Single Read. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
FBWx Flatten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
FSWx Flatten Single Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat write cycles. The encoding of this field is
shown in the table below.
http://www.motorola.com/computer/literature 2-73
2
6
2
7
2
8
2
9
3
0
3
1
ENA
R
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
FBR/FSR/FBW/FSW Effects on Bus Pipelining
00 None
01 None
10 Flatten always
11 Flatten if switching masters
2