MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Hawk Internal Error Interrupt Destination Register
Offset $10210
Bit 3
1
3
0
2
9
2
8
2
7
2
6
This register indicates the possible destinations for the Hawk internal error
interrupt source. These interrupts operate in the Distributed interrupt
delivery mode.
P1 PROCESSOR 1. The interrupt is pointed to processor 1.
P0 PROCESSOR 0. The interrupt is pointed to processor 0.
Interprocessor Interrupt Dispatch Registers
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
There are four Interprocessor Interrupt Dispatch Registers. Writing to an
IPI Dispatch Register with the P0 and/or P1 bit set causes an interprocessor
interrupt request to be sent to one or more processors. Note that each IPI
Dispatch Register has two addresses. These registers are considered to be
per processor registers and there is one address per processor. Reading
these registers returns zeros.
P1 PROCESSOR 1. The interrupt is directed to processor 1.
P0 PROCESSOR 0. The interrupt is directed to processor 0.
2-126 Computer Group Literature Center Web Site
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name HAWK INTERNAL ERROR INTERRUPT DESTINATION
Operation R R R R
Reset $00 $00 $00 $00 0
Offset Processor 0 $20040, $20050, $20060, $20070
Processor 1 $21040, $21050,$21060, $21070
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
Name IPI DISPATCH
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
P0
P1
R/W
R/W
0
1
0 9 8 7 6 5 4 3 2 1 0
Operation R R R R
Reset $00 $00 $00 $00 0
P0
P1
W
W
0