MVME5100 Single Board Computer Programmer's Reference Guide

CSR’s Readability
Multi-Processor Interrupt Controller (MPIC)
Unless explicitly specified, all registers are readable and return the last
value written. The exceptions are the IPI dispatch registers and the EOI
registers which return zeros on reads, the interrupt source ACT bit which
returns current interrupt source status, the interrupt acknowledge register,
which returns the vector of the highest priority interrupt which is currently
pending, and reserved bits which returns zeros. The interrupt acknowledge
register is also the only register which exhibits any read side-effects.
Interrupt Source Priority
Each interrupt source is assigned a priority value in the range from 0 to 15
where 15 is the highest. In order for delivery of an interrupt to take place,
the priority of the source must be greater than that of the destination
processor. Therefore, setting a source priority to zero inhibits that
interrupt.
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