MVME5100 Single Board Computer Programmer's Reference Guide

PCI Registers
3
1
3
0
2
9
2
8
2
7
2
6
2
5
Registers
The PCI Configuration Registers are compliant with the configuration
register set described in the PCI Local Bus Specification, Revision 2.1.
The CONFIG_ADDRESS and CONFIG_DATA registers described in
this section are accessed from the PPC bus within PCI I/O space.
All write operations to reserved registers will be treated as no-ops. That is,
the access will be completed normally on the bus and the data will be
discarded. Read accesses to reserved or unimplemented registers will be
completed normally and a data value of 0 will be returned.
The PCI Configuration Register map of the PHB is shown in Table 2-17.
The PCI I/O Register map of the PHB is shown in Table 2-18
2
4
2
3
Table 2-17. PCI Configuration Register
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
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