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MVME5100 Single Board Computer Programmer's Reference Guide

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IPI Vector/Priority Registers<br />

Offset IPI 0 - $010A0<br />

IPI 1 - $010B0<br />

IPI 2 - $010C0<br />

IPI 3 - $010D0<br />

Bit 3<br />

1<br />

3<br />

0<br />

2<br />

9<br />

2<br />

8<br />

2<br />

7<br />

2<br />

6<br />

2<br />

5<br />

2<br />

4<br />

Name IPI VECTOR/PRIORITY<br />

Operation<br />

Reset<br />

ACT<br />

MASK<br />

R<br />

R/W<br />

0<br />

1<br />

2<br />

3<br />

2<br />

2<br />

2<br />

1<br />

2<br />

0<br />

1<br />

9<br />

1<br />

8<br />

Registers<br />

MASK MASK. Setting this bit disables any further interrupts<br />

from this source. If the mask bit is cleared while the bit<br />

associated with this interrupt is set in the IPR, the interrupt<br />

request will be generated.<br />

ACT ACTIVITY. The activity bit indicates that an interrupt<br />

has been requested or that it is in-service. The ACT bit is<br />

set to a one when its associated bit in the Interrupt Pending<br />

Register or In-Service Register is set.<br />

PRIOR PRIORITY. Interrupt priority 0 is the lowest and 15 is<br />

the highest. Note that a priority level of 0 will not enable<br />

interrupts.<br />

VECTOR VECTOR. This vector is returned when the Interrupt<br />

Acknowledge register is examined during a request for<br />

the interrupt associated with this vector.<br />

http://www.motorola.com/computer/literature 2-117<br />

1<br />

7<br />

1<br />

6<br />

1<br />

5<br />

1<br />

4<br />

1<br />

3<br />

1<br />

2<br />

1<br />

1<br />

1<br />

0 9 8 7 6 5 4 3 2 1 0<br />

PRIOR VECTOR<br />

R R/W R R/W<br />

$000 $0 $00 $00<br />

2

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