MVME5100 Single Board Computer Programmer's Reference Guide

PPC Arbiter
Pin Name
Functional Description
The PHB has an internal PPC60x bus arbiter. The use of this arbiter is
optional. If the internal arbiter is disabled, then the PHB must be allowed
to participate in an externally implemented PPC60x arbitration
mechanism. The selection of either internal or external PPC arbitration
mode is made by sampling an RD line at the release of reset. Refer to the
section titled PHB Hardware Configuration in this chapter for more
information.
The PHB has been designed to accommodate up to four PPC60x bus
masters, including itself (HAWK), two processors (CPU0/CPU1), and an
external PPC60x master (EXTL). EXTL can be a L2 cache, a second
bridge chip, etc. When the PPC Arbiter is disabled, PHB generates an
external request and listen for an external grant for itself. It also listens to
the other external grants to determine the PPC60x master identification
field (XID) within the GCSR. When the PPC Arbiter is enabled, the PHB
receives requests and issue grants for itself and for the other three bus
masters. The XID field is determined by the PPC Arbiter.
The PPC60x arbitration signals and their functions are summarized in
Table 2-6.
Pin
Type
Table 2-6. PPC Arbiter Pin Assignments
Reset
Internal Arbiter External Arbiter
Direction Function Direction Function
XARB0 BiDir Tristate Output CPU0 Grant_ Input CPU0 Grant_
XARB1 BiDir Tristate Output CPU1 Grant_ Input CPU1 Grant_
XARB2 BiDir Tristate Output EXTL Grant_ Input EXTL Grant_
XARB3 BiDir Tristate Input CPU0 Request_ Output HAWK Request_
XARB4 Input - - Input CPU1 Request_ Input HAWK Grant_
XARB5 Input - - Input EXTL Request_ Input - -
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