MVME5100 Single Board Computer Programmer's Reference Guide

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xii Error Logging............................................................................................ 3-13 ROM/Flash Interface........................................................................................ 3-14 ROM/Flash Speeds.................................................................................... 3-19 I2C Interface..................................................................................................... 3-22 I2C Byte Write .......................................................................................... 3-23 I2C Random Read ..................................................................................... 3-25 I2C Current Address Read ........................................................................ 3-27 I2C Page Write.......................................................................................... 3-29 I2C Sequential Read.................................................................................. 3-31 Refresh/Scrub ................................................................................................... 3-34 CSR Accesses................................................................................................... 3-34 External Register Set ........................................................................................ 3-34 Chip Configuration........................................................................................... 3-35 Programming Model................................................................................................ 3-35 CSR Architecture ............................................................................................. 3-35 Register Summary ............................................................................................ 3-36 Detailed Register Bit Descriptions ................................................................... 3-38 Vendor/Device Register ............................................................................ 3-39 Revision ID/General Control Register ...................................................... 3-39 SDRAM Enable and Size Register (Blocks A, B, C, D)........................... 3-41 SDRAM Base Address Register (Blocks A/B/C/D) ................................. 3-43 CLK Frequency Register........................................................................... 3-44 ECC Control Register ............................................................................... 3-46 Error Logger Register ............................................................................... 3-50 Error_Address Register............................................................................. 3-52 Scrub/Refresh Register.............................................................................. 3-52 Scrub Address Register ............................................................................. 3-53 ROM A Base/Size Register....................................................................... 3-54 ROM B Base/Size Register....................................................................... 3-57 ROM Speed Attributes Registers .............................................................. 3-59 Data Parity Error Log Register ................................................................. 3-61 Data Parity Error Address Register........................................................... 3-62 Data Parity Error Upper Data Register ..................................................... 3-62 Data Parity Error Lower Data Register..................................................... 3-63 I2C Clock Prescaler Register .................................................................... 3-64 I2C Control Register ................................................................................. 3-64 I2C Status Register.................................................................................... 3-65 I2C Transmitter Data Register .................................................................. 3-66 I2C Receiver Data Register....................................................................... 3-67 SDRAM Enable and Size Register (Blocks E,F,G,H) .............................. 3-67 SDRAM Base Address Register (Blocks E/F/G/H).................................. 3-68 SDRAM Speed Attributes Register .......................................................... 3-69
Address Parity Error Log Register ............................................................3-71 Address Parity Error Address Register......................................................3-72 32-Bit Counter ...........................................................................................3-73 External Register Set .................................................................................3-73 tben Register..............................................................................................3-74 Software Considerations ..........................................................................................3-75 Programming ROM/Flash Devices...................................................................3-75 Writing to the Control Registers .......................................................................3-75 Initializing SDRAM Related Control Registers ...............................................3-76 SDRAM Speed Attributes .........................................................................3-76 SDRAM Size .............................................................................................3-77 I2C EEPROMs ..........................................................................................3-77 SDRAM Base Address and Enable ...........................................................3-77 SDRAM Control Registers Initialization Example ...................................3-78 Optional Method for Sizing SDRAM........................................................3-84 ECC Codes...............................................................................................................3-87 CHAPTER 4 Hawk Programming Details Introduction................................................................................................................4-1 PCI Arbitration...........................................................................................................4-1 Hawk MPIC External Interrupts .........................................................................4-1 8259 Interrupts....................................................................................................4-3 Exceptions..................................................................................................................4-5 Sources of Reset..................................................................................................4-5 Soft Reset............................................................................................................4-5 CPU Reset...........................................................................................................4-5 Error Notification and Handling.........................................................................4-6 Endian Issues .............................................................................................................4-7 Processor/Memory Domain ................................................................................4-9 MPIC’s Involvement...........................................................................................4-9 PCI Domain ........................................................................................................4-9 APPENDIX A Related Documentation Motorola <strong>Computer</strong> Group Documents ....................................................................A-1 Manufacturers’ Documents.......................................................................................A-2 Related Specifications...............................................................................................A-4 xiii
Page 1 and 2: MVME5100 Single Board Computer Prog
Page 3 and 4: Safety Summary The following genera
Page 5 and 6: CE Notice (European Community) Moto
Page 7 and 8: Contents About This Manual Summary
Page 9 and 10: PCI Slave .........................
Page 11: Spurious Vector Register...........
Page 15: List of Figures Figure 1-1. MVME510
Page 18 and 19: xviii Table 2-13. Address Modificat
Page 21 and 22: About This Manual The MVME5100 Sing
Page 23 and 24: Part Number Description MVME761-011
Page 25 and 26: 8259 Interrupts, and a description
Page 27: In this manual, assertion and negat
Page 30 and 31: 1 Product Data and Memory Maps Main
Page 32 and 33: 1 Product Data and Memory Maps Memo
Page 34 and 35: 1 Product Data and Memory Maps Tabl
Page 36 and 37: 1 Product Data and Memory Maps PCI
Page 38 and 39: 1 Product Data and Memory Maps L2 C
Page 40 and 41: 1 Product Data and Memory Maps conn
Page 42 and 43: 1 Product Data and Memory Maps to i
Page 44 and 45: 1 Product Data and Memory Maps Requ
Page 46 and 47: 1 Product Data and Memory Maps PROC
Page 48 and 49: 1 Product Data and Memory Maps The
Page 50 and 51: 1 Product Data and Memory Maps Tabl
Page 52 and 53: 1 Product Data and Memory Maps Stat
Page 54 and 55: 1 Product Data and Memory Maps MODR
Page 56 and 57: 1 Product Data and Memory Maps NVRA
Page 58 and 59: 1 Product Data and Memory Maps Geog
Page 60 and 61: 1 Product Data and Memory Maps Boar
Page 62 and 63:
1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
Page 66 and 67:
1 Product Data and Memory Maps IDRE
Page 69 and 70:
2Hawk PCI Host Bridge & Multi- Proc
Page 71 and 72:
Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
Page 79 and 80:
Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
Page 85 and 86:
PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
Page 103 and 104:
Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Page 127 and 128:
Program Visible Registers Multi-Pro
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Page 131 and 132:
Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
Page 175 and 176:
Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
Page 179 and 180:
3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
Page 193 and 194:
Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
Page 213 and 214:
Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
Page 231 and 232:
Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
Page 251 and 252:
Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
Page 259 and 260:
Data Parity Error Lower Data Regist
Page 261 and 262:
I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
Page 265 and 266:
SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
Page 271 and 272:
Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
Page 291 and 292:
Endian Issues Hawk Endian Issues Th
Page 293:
Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
Page 298 and 299:
A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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Page 314 and 315:
Page 316 and 317:
C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
Page 327 and 328:
om_a_rv and rom_b_rv encoding 3-55
Page 329:
VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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