MVME5100 Single Board Computer Programmer's Reference Guide
MVME5100 Single Board Computer Programmer's Reference Guide
MVME5100 Single Board Computer Programmer's Reference Guide
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I<br />
N<br />
D<br />
E<br />
X<br />
SDRAM Enable and Size Register 3-41,<br />
3-67<br />
SDRAM Speed Attributes Register 3-69<br />
Vendor/Device Register 3-39<br />
SMC Data Parity Error Address Register<br />
3-62<br />
SMC Data Parity Error Log Register 3-61<br />
SMC Data Parity Error Lower Data Register<br />
3-63<br />
SMC External Register Set 3-73<br />
SMC Scrub Address Register 3-53<br />
SMC tben Register 3-74<br />
soft reset<br />
MPIC 4-5<br />
software considerations 3-75<br />
Hawk 3-75<br />
Software Readable Header Register 1-29<br />
sources of reset<br />
<strong>MVME5100</strong> 4-5<br />
SPD 3-77<br />
SPD JEDEC standard definition 1-12<br />
Speculative PCI Request 2-47<br />
spread I/O addressing<br />
as function of PHB 2-30<br />
Spurious Vector Register 2-118<br />
SRAM base address 3-35<br />
status bit descriptions 3-38<br />
Status Register 1-23, 1-24<br />
strap pins configuration for the<br />
PC87308VUL 1-34<br />
swen 3-52<br />
syndrome codes ordered by bit in error 3-87<br />
System Bus 1-8<br />
System Controller Mode bit 1-24<br />
System Memory Controller (SMC) 3-1<br />
T<br />
TA<br />
as used with PPC Slave 2-7<br />
Table 2-10<br />
Table 2-2. 2-10<br />
target initiated termination<br />
Index<br />
2-24<br />
TBEN Bit Register 1-27<br />
tben Register<br />
SMC 3-74<br />
Timer Basecount Registers 2-120<br />
Timer Current Count Registers 2-119<br />
Timer Destination Registers 2-122<br />
Timer Frequency Register 2-118<br />
Timer Vector/Priority Registers 2-121<br />
timing (ROM/Flash access) 3-19<br />
transaction(s)<br />
burst 2-8<br />
compelled 2-7<br />
instance of interrupt 2-8<br />
ordering 2-48<br />
PCI originated/PPC bound described 2-5<br />
posted 2-7<br />
PPC originated/PCI bound described 2-4<br />
transactions<br />
PPC Slave limits 2-8<br />
unable to retry 2-8<br />
transfer types<br />
generated by PPC Master 2-14<br />
PCI command code dependent 2-14<br />
PPC60x bus 2-14<br />
triple- (or greater) bit error 3-12<br />
Tundra Universe Controller 1-2<br />
U<br />
Universe ASIC 1-17<br />
Universe chip problems after a PCI reset 4-5<br />
Universe VMEbus interface ASIC 1-8, 1-15<br />
User configuration Data 1-13<br />
V<br />
Vendor ID/ Device ID Registers 2-98<br />
Vendor ID/Device ID Registers 2-70<br />
Vendor Identification Register 2-116<br />
Vendor/Device Register<br />
SMC 3-39<br />
Vital Product Data 1-10, 1-13<br />
Vital Product Data (VPD) B-1<br />
IN-10 <strong>Computer</strong> Group Literature Center Web Site
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