MVME5100 Single Board Computer Programmer's Reference Guide

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3 Syndrome System Memory Controller (SMC) Bit Syndrome Table 3-22. Single Bit Errors Ordered by Syndrome Code Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome $00 - $20 ckd5 $40 ckd6 $60 - $80 ckd7 $A0 - $C0 - $E0 rd45 $01 ckd0 $21 - $41 - $61 rd42 $81 - $A1 rd38 $C1 rd37 $E1 - $02 ckd1 $22 - $42 - $62 rd41 $82 - $A2 rd35 $C2 rd34 $E2 - $03 - $23 rd31 $43 rd30 $63 - $83 rd29 $A3 - $C3 - $E3 - $04 ckd2 $24 - $44 - $64 rd55 $84 - $A4 rd32 $C4 rd33 $E4 - $05 - $25 rd8 $45 rd27 $65 - $85 rd26 $A5 - $C5 - $E5 - $06 - $26 rd9 $46 rd23 $66 - $86 rd22 $A6 - $C6 - $E6 - $07 rd21 $27 - $47 - $67 - $87 - $A7 rd52 $C7 - $E7 - $08 ckd3 $28 - $48 - $68 rd54 $88 - $A8 rd51 $C8 rd47 $E8 - $09 - $29 rd48 $49 rd24 $69 - $89 rd25 $A9 - $C9 - $E9 rd4 $0A - $2A rd3 $4A rd0 $6A - $8A rd19 $AA - $CA - $EA - $0B rd18 $2B - $4B - $6B - $8B - $AB - $CB - $EB - $0C - $2C rd2 $4C rd1 $6C - $8C rd15 $AC - $CC - $EC - $0D rd14 $2D - $4D - $6D - $8D - $AD - $CD - $ED - $0E rd13 $2E - $4E - $6E - $8E - $AE - $CE - $EE - $0F - $2F - $4F rd44 $6F - $8F - $AF - $CF - $EF - $10 ckd4 $30 - $50 - $70 rd53 $90 - $B0 rd50 $D0 rd46 $F0 - $11 - $31 rd49 $51 rd43 $71 - $91 rd39 $B1 - $D1 - $F1 - $12 - $32 rd63 $52 rd40 $72 - $92 rd16 $B2 - $D2 - $F2 - $13 rd17 $33 - $53 - $73 - $93 - $B3 - $D3 rd60 $F3 - $14 - $34 rd62 $54 rd59 $74 - $94 rd56 $B4 - $D4 - $F4 rd12 $15 rd11 $35 - $55 - $75 - $95 - $B5 - $D5 - $F5 - $16 rd10 $36 - $56 - $76 - $96 - $B6 - $D6 - $F6 - $17 - $37 - $57 - $77 - $97 - $B7 - $D7 - $F7 - $18 - $38 rd61 $58 rd58 $78 - $98 rd57 $B8 - $D8 - $F8 - $19 rd7 $39 - $59 - $79 - $99 - $B9 - $D9 - $F9 - $1A rd6 $3A - $5A - $7A rd20 $9A - $BA - $DA - $FA - $1B - $3B - $5B - $7B - $9B - $BB - $DB - $FB - $1C rd5 $3C - $5C - $7C - $9C - $BC - $DC - $FC - $1D - $3D rd28 $5D - $7D - $9D - $BD - $DD - $FD - $1E - $3E - $5E - $7E - $9E rd36 $BE - $DE - $FE - $1F - $3F - $5F - $7F - $9F - $BF - $DF - $FF - 3-88 Computer Group Literature Center Web Site Bit
4Hawk Programming Details Introduction PCI Arbitration 4 This chapter contains details of several programming functions associated with the Hawk ASIC chip. PCI arbitration must be provided by the host board. Hawk MPIC External Interrupts MPIC IRQ The MVME5100 Hawk MPIC is fully compliant with the industry standard Multi-Processor Interrupt Controller Specification. Following a power-up reset, the MPIC is configured to operate in the parallel interrupt delivery mode on the MVME5100 series: Edge/ Level Table 4-1. MPIC Interrupt Assignments Polarity Interrupt Source Notes IRQ0 Level High PIB (8259) from IPMC761 in PMC Slot 1 3 IRQ1 Level Low TL16C550 UART Serial Port 1, 2 1, 4 IRQ2 Level Low PCI-Ethernet Device Port 1 (Front panel) IRQ3 Level Low Hawk WDT1O_L / WDT2O_L 5 IRQ4 Level Low Thermal Alarm output (TOUT) of Dallas Semiconductor DS1621 IRQ5 Level Low PCI-VME INT 0 (Universe LINT0#) 2 IRQ6 Level Low PCI-VME INT 1 (Universe LINT1#) 2 IRQ7 Level Low PCI-VME INT 2 (Universe LINT2#) 2 IRQ8 Level Low PCI-VME INT 3 (Universe LINT3#) 2 6 4-1
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
Page 233 and 234: FEF80070 DPE_A FEF80078 DPE_DH FEF8
Page 235 and 236: Vendor/Device Register Address $FEF
Page 237 and 238: SDRAM Enable and Size Register (Blo
Page 239 and 240: SDRAM Base Address Register (Blocks
Page 241 and 242: drr value Programming Model us (64
Page 243 and 244: Normal View of Data (rwcb=0) Check-
Page 245 and 246: ! Caution Programming Model sien Wh
Page 247 and 248: Programming Model esbt esbt is set
Page 249 and 250: Scrub Address Register Programming
Page 251 and 252: Programming Model each half of the
Page 253 and 254: ROM B Base/Size Register Address Bi
Page 255 and 256: ROM Speed Attributes Registers Prog
Page 257 and 258: Data Parity Error Log Register Addr
Page 259 and 260: Data Parity Error Lower Data Regist
Page 261 and 262: I 2 C Status Register Programming M
Page 263 and 264: I 2 C Receiver Data Register Addres
Page 265 and 266: SDRAM Speed Attributes Register Pro
Page 267 and 268: Programming Model swr_dpl swr_dpl c
Page 269 and 270: 32-Bit Counter Address $FEF80100 Bi
Page 271 and 272: Software Considerations When the tb
Page 273 and 274: SDRAM Size I 2 C EEPROMs Software C
Page 275 and 276: Software Considerations c. If a CAS
Page 277 and 278: Software Considerations Notes 1. Us
Page 279 and 280: Software Considerations 8. Now that
Page 281 and 282: 2. For each of the Blocks A through
Page 283: ECC Codes ECC Codes When the Hawk r
Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
Page 289 and 290: Exceptions Sources of Reset Soft Re
Page 291 and 292: Endian Issues Hawk Endian Issues Th
Page 293: Processor/Memory Domain MPIC’s In
Page 296 and 297: A Manufacturers’ Documents Manufa
Page 298 and 299: A Related Specifications Related Sp
Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 316 and 317: C Introduction The MVME2700 board,
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323 and 324: L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 325 and 326: devices, when Big-Endian 2-38 Maste
Page 327 and 328: om_a_rv and rom_b_rv encoding 3-55
Page 329: VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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