MVME5100 Single Board Computer Programmer's Reference Guide

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2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond valid decoded cycles as a medium responder. Target Initiated Termination The PCI Slave normally strives to complete transactions without issuing disconnects or retries. There are four exceptions where the PCI Slave performs a disconnect: ❏ All burst configuration cycles are terminated with a disconnect after one data beat has been transferred. ❏ All transactions that have a byte enable hole are disconnected. ❏ All transactions attempting to perform non-linear addressing mode are terminated with a disconnect after one data beat is transferred. ❏ A transaction that crosses from a valid PHB decode space to an invalid PHB decode space is disconnected. Note that this does not include crossing contiguous multiple map decoder space, in which case PHB does not issue a disconnect. There are two exceptions where the PCI Slave performs a retry (disconnect with no data transfer): ❏ While within a lock sequence, the PCI Slave retries all non-locking masters. ❏ At the completion of a lock sequence between the times the two locks are released on the PCI bus and the PPC bus. All accesses to the PCI Slave, regardless of who is master is will be retried. Delayed Transactions The PCI Slave does not participate in the delayed transaction protocol. 2-24 <strong>Computer</strong> Group Literature Center Web Site
Fast Back-to-Back Transactions Functional Description The PCI Slave supports both of the fundamental target requirements for fast back-to-back transactions. The PCI Slave meets the first criteria of being able to successfully track the state of the PCI bus without the existence of an IDLE state between transactions. The second criteria associate with signal turn-around timing is met by default since the PCI Slave functions as a medium responder. Latency The PCI Slave does not have any hardware mechanisms in place to guarantee that the initial and subsequent target latency requirements are met. Typically this is not a problem since the bandwidth of the PPC bus far exceeds the bandwidth of the PCI bus. Exclusive Access The PCI Slave fully supports the PCI lock function. From the perspective of the PPC bus, the PHB enables a lock to a single 32 byte cache line. When a cache line has been locked, the PHB snoops all transactions on the PPC bus. If a snoop hit happens, the PHB retries the transaction. Note that the retry is ‘benign’ since there is no follow-on transaction after the retry is asserted. The PHB contiues to snoop and retry all accesses to the locked cache line until a valid ‘unlock’ is presented to the PHB and the last locked cache line transaction is successfully executed. Note that the PHB locks the cache line that encompasses the actual address of the locked transaction. For example, a locked access to offset 0x28 creates a lock on the cache line starting at offset 0x20. From the perspective of the PCI bus, the PCI Slave locks the entire resource. Any attempt by a non-locking master to access any PCI resource represented by the PHB results in the PCI Slave issuing a retry. Parity The PCI Slave supports address parity error detection, data parity generation, and data parity error detection. Cache Support The PCI Slave does not participate in the PCI caching protocol. http://www.motorola.com/computer/literature 2-25 2
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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Page 62 and 63: 1 Product Data and Memory Maps IPMC
Page 64 and 65: 1 Product Data and Memory Maps Z853
Page 66 and 67: 1 Product Data and Memory Maps IDRE
Page 69 and 70: 2Hawk PCI Host Bridge & Multi- Proc
Page 71 and 72: Block Diagram PCI Bus MPIC Interfac
Page 73 and 74: PPC Bus Interface Functional Descri
Page 75 and 76: PPC Slave Functional Description Ea
Page 77 and 78: PPC FIFO PPC Transfer Type Transfer
Page 79 and 80: Functional Description Table 2-2. P
Page 81 and 82: Table 2-4. PPC Master Read Ahead Op
Page 83 and 84: PPC Arbiter Pin Name Functional Des
Page 85 and 86: PPC Parity Functional Description T
Page 87 and 88: PCI Bus Interface PCI Address Mappi
Page 89 and 90: Functional Description Each map dec
Page 91: Command Types: Functional Descripti
Page 95 and 96: Functional Description It should be
Page 97 and 98: Functional Description The PCI Mast
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Page 101 and 102: Functional Description The device t
Page 103 and 104: Functional Description The Hawk’s
Page 105 and 106: Functional Description Notes 1. “
Page 107 and 108: . DH07-00 DH15-08 DH23-16 DH31-24 F
Page 109 and 110: Error Handling Functional Descripti
Page 111 and 112: Functional Description When not bei
Page 113 and 114: Functional Description PPC1-Bug>md
Page 115 and 116: Functional Description From the per
Page 117 and 118: Functional Description ❏ Write po
Page 119 and 120: Multi-Processor Interrupt Controlle
Page 121 and 122: CSR’s Readability Multi-Processor
Page 123 and 124: Interprocessor Interrupts (IPI) 825
Page 127 and 128: Program Visible Registers Multi-Pro
Page 131 and 132: Reset State Multi-Processor Interru
Page 133 and 134: EOI Register Multi-Processor Interr
Page 135 and 136: Registers Registers This section pr
Page 137 and 138: Bit ---> Table 2-16. PPC Register M
Page 139 and 140: General Control-Status/Feature Regi
Page 141 and 142: PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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