MVME5100 Single Board Computer Programmer's Reference Guide

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C Introduction The MVME2700 board, which uses a PReP memory map, is configured in this example to occupy address space from 1000 0000 to 13FF FFFF (64MB) on the VMEbus. The MVME5100, which defaults to a CHRP memory map, occupies another 64MB address range, which in this example is from 1400 0000 to 17FF FFFF. The PCI Slave Images represent the view of the Universe on the PCI Local Bus. The VME Slave Images represent the view of the Universe on the VMEbus. The purpose of this application note is to demonstrate the process used to select the appropriate Base and Bound values for the desired address mapping. In this case, the entire 64MB of available memory space on the board has been selected. The memory can be segmented by selecting different sizes and mapping them using the remaining slave images within the Universe device. In addition, by using the appropriate settings in the Control register, the memory can be mapped as A24/D16, A16/D8, or other desired addressing. Once the Base and Bound values are determined, the correct value for the Translate register must be selected so that the address presented to the bus on the other side of the Universe is correct. Each of the Translate register’s values were determined as follows: 2700 PCI Slave Translate In the default memory map, PCI Memory space begins at C000 0000, the first 1MB (100 0000) is set aside for other devices on the PCI Local Bus that require PCI Memory. PowerPC addresses from C000 0000 to DFFF FFFF are presented, zero based, on the PCI Local Bus. The Universe is configured to accept PCI Memory addresses from 0100 0000 to 2000 0000 in PCI Slave Image 1. These addresses are passed unchanged to the VMEbus. To translate a presented PCI address to a zero based VMEbus address, the translation value of FF00 0000 was chosen. This value is the required translation to make the presented address (0100 0000) become 0000 0000 on the VMEbus: 0100 0000 + FF00 0000 => 1 0000 0000. 2700 VME Slave Translate For the VME Slave register, the Universe passes the presented address unchanged onto the PCI Local Bus, unless translation is applied. Consulting the memory maps available in the appropriate MVME Programmer’s Guide, one finds that PowerPC memory is located at 8000 C-2 Computer Group Literature Center Web Site
VMEbus Mapping Example 0000 on the PCI Local bus. Thus, to translate an inbound address of 1000 0000 (the configured VMEbus Base address of this board to 8000 0000, which is presented to DRAM as 0000 0000 and translation value of 7000 0000 is selected: 1000 0000 + 7000 0000 => 8000 0000 on the PCI Local Bus that becomes 0000 0000 on the PowerPC bus. 5100 PCI Slave Translate In the CHRP memory map, PCI Memory Space is based at 8000 0000. Once again, the first 1MB is reserved for other PCI devices requiring memory space so the Universe is configured to claim addresses from 8100 0000 to A000 0000 that appear on the PCI Local Bus. Because this is a CHRP memory map, the address presented on the PCI Local Bus is not translated, so a PPC generated address of 8100 0000 appears on the PCI Local Bus as 8100 0000. Again, the same translation calculation is required to adjust this address to be presented as 0000 0000 on the VMEbus. In this case, the value is 7F00 0000: 8100 0000 + 7F00 0000 => 1 0000 0000. 5100 VME Slave Translation In the CHRP memory map, DRAM is located at 0000 0000 on the PCI Local Bus. As configured, the Universe accepts VMEbus addresses between 1400 0000 and 17FF FFFF. To translate a VMEbus address of 1400 0000 to 0000 0000 on the PCI Local Bus a translation offset of EC00 0000 is chosen: 1400 0000 +EC00 0000 => 1 0000 0000. Once again, the overflow results in the desired value. http://www.mcg.mot.com/literature C-3 C
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
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Functional Description ❏ Write po
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Multi-Processor Interrupt Controlle
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CSR’s Readability Multi-Processor
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Interprocessor Interrupts (IPI) 825
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Program Visible Registers Multi-Pro
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Reset State Multi-Processor Interru
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EOI Register Multi-Processor Interr
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Registers Registers This section pr
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Bit ---> Table 2-16. PPC Register M
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General Control-Status/Feature Regi
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PPC Arbiter/PCI Arbiter Control Reg
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Registers PRKx Parking. This field
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Hardware Control-Status/Prescaler A
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PPC Error Test/Error Enable Registe
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Registers XBTOI PPC Address Bus Tim
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Registers PPER PCI Parity Error. Th
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PPC Error Attribute Register Regist
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PCI Interrupt Acknowledge Register
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PPC Slave Offset/Attribute (0, 1 an
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The fields within XSADD3 are define
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Registers KEY Key. This field is us
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PPC6-Bug>mw feff0068 aa88;h Effecti
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PCI Registers 3 1 3 0 2 9 2 8 2 7 2
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PCI Command/ Status Registers Regis
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Revision ID/ Class Code Registers O
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The MPIC Memory Base Address Regist
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Registers INV Invalidate Enable. If
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Conceptual perspective from the PCI
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Registers CONFIG_DATA Register The
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3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
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3 1 3 0 2 9 2 8 2 7 Feature Reporti
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Registers M CASCADE MODE. Allows ca
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IPI Vector/Priority Registers Offse
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Timer Current Count Registers Offse
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Timer Vector/Priority Registers Off
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Registers MASK MASK. Setting this b
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Hawk Internal Error Interrupt Vecto
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Current Task Priority Registers Off
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3System Memory Controller (SMC) Int
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PowerPC Side D[0:63] DP[0:7] Correc
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Figure 3-4. Hawk’s System Memory
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Page Holding SDRAM Speeds Functiona
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SDRAM Organization Functional Descr
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Cache Coherency Functional Descript
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Error Logging Functional Descriptio
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Functional Description When the wid
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Table 3-4. PPC60x to ROM/Flash (64
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ROM/Flash Speeds ACCESS TYPE Functi
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ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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Page 267 and 268: Programming Model swr_dpl swr_dpl c
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Page 281 and 282: 2. For each of the Blocks A through
Page 283 and 284: ECC Codes ECC Codes When the Hawk r
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Page 287 and 288: 8259 Interrupts PRI PSIO IRQ Input
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Page 291 and 292: Endian Issues Hawk Endian Issues Th
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Page 296 and 297: A Manufacturers’ Documents Manufa
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Page 300 and 301: B MVME5100 VPD Reference Informatio
Page 319 and 320: Numerics 32-Bit Counter 3-73 SMC 3-
Page 321 and 322: E ECC Codes Hawk 3-87 SMC 3-11 ECC
Page 323 and 324: L L2 Cache 1-1, 1-9 L2 Cache SRAM S
Page 325 and 326: devices, when Big-Endian 2-38 Maste
Page 327 and 328: om_a_rv and rom_b_rv encoding 3-55
Page 329: VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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