MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
SDRAM Control Registers Initialization Example
The following is a possible sequence for initializing SDRAM control
registers:
1. Get a small piece of SDRAM for software to use for this routine
(optional).
This routine assumes that SDRAM related control bits are still at the
power-up-reset default settings. We will use a small enough piece of
SDRAM that the address signals that are affected by SDRAM size
will not matter.
For each SDRAM block:
a. Set the block’s base address to some even multiple of 32MB
(refer to the section titled SDRAM Base Address Register
(Blocks A/B/C/D) for more information.)
b. Set the block’s size to 4Mx16 and enable it (refer to the section
titled SDRAM Enable and Size Register (Blocks A,B,C,D) for
more information.)
c. Test the first 1MB of the block.
d. If the test fails, disable the block, clear its size to 0MB, disable it
and then repeat steps 1 through 5 with the next block. If the test
passes, go ahead and use the first 1M of the block.
2. Using the I 2 C bus, determine which memory blocks are present.
Using the addressing scheme established by the board designer,
probe for SPD’s to determine which blocks of SDRAM are present.
SPD byte 0 could be used to determine SPD presence. SPD Byte 5
indicates the number of SDRAM blocks that belong to an SPD.
3. Obtain the CAS latency information for all blocks that are present
to determine whether to set or to clear the cl3 bit.
For each SDRAM block that is present:
a. Check SPD byte 18 to determine which CAS latencies are
supported.
b. If a CAS latency of 2 is supported, then go to Step 3. Otherwise,
a CAS latency of 3 is all that is supported for this block.
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