MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Timers
There is a divide by eight pre scaler which is synchronized to the PCI
clock. The output of the pre scaler enables the decrement of the four timers.
The timers may be used for system timing or to generate periodic
interrupts. Each timer has four registers, which are used for configuration
and control. They are:
❏ Current Count Register
❏ Base Count Register
❏ Vector-Priority Register
❏ Destination Register
Interrupt Delivery Modes
The direct and distributed interrupt delivery modes are supported. Note
that the direct delivery mode has sub modes of multicast or non-multicast.
The IPIs and Timer interrupts operate in the direct delivery mode. The
externally sourced, or I/O interrupts operate in the distributed mode.
In the direct delivery mode, the interrupt is directed to one or both
processors. If it is directed to two processors (i.e., multicast), it will be
delivered to two processors. The interrupt is delivered to the processor
when the priority of the interrupt is greater than the priority contained in
the task register for that processor, and when the priority of the interrupt is
greater than any interrupt which is in-service for that processor. An
interrupt is considered to be in service from the time its vector is returned
during an interrupt acknowledge cycle until an EOI is received for that
interrupt. The EOI cycle indicates the end of processing for the highest
priority in service interrupt.
2-56 Computer Group Literature Center Web Site