MVME5100 Single Board Computer Programmer's Reference Guide

I 2 C Byte Write
Functional Description
The I 2 C Status Register contains the i 2 _cmplt bit which is used to indicate
if the I 2 C master controller is ready to perform an operation. Therefore, the
first step in the programming sequence should be to test the i 2 _cmplt bit
for the operation-complete status. The next step is to initiate a start
sequence by first setting the i 2 start and i 2 enbl bits in the I 2 C Control
Register and then writing the device address (bits 7-1) and write bit (bit
0=0) to the I 2 C Transmitter Data Register. The i 2 _cmplt bit will be
automatically clear with the write cycle to the I 2 C Transmitter Data
Register. The I 2 C Status Register must now be polled to test the i 2 _cmplt
and i 2 _ackin bits. The i 2 _cmplt bit becomes set when the device address
and write bit have been transmitted, and the i 2 _ackin bit provides status as
to whether or not a slave device acknowledged the device address. With
the successful transmission of the device address, the word address will be
loaded into the I 2 C Transmitter Data Register to be transmitted to the slave
device. Again, i 2 _cmplt and i2_ackin bits must be tested for proper
response. After the word address is successfully transmitted, the next data
loaded into the I 2 C Transmitter Data Register will be transferred to the
address location selected previously within the slave device. After
i 2 _cmplt and i 2 _ackin bits have been tested for proper response, a stop
sequence must be transmitted to the slave device by first setting the i 2 stop
and i 2 enbl bits in the I 2 C Control Register and then writing a dummy data
(data=don’t care) to the I 2 C Transmitter Data Register. The I 2 C Status
Register must now be polled to test i 2 _cmplt bit for the operation-complete
status. The stop sequence will initiate a programming cycle for the serial
EEPROM and also relinquish the ASIC master’s possession of the I 2 C bus.
Figure 3-5 shows the suggested software flow diagram for programming
the I 2 C byte write operation.
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