MVME5100 Single Board Computer Programmer's Reference Guide

om_a_rv and rom_b_rv encoding 3-55
rom_a_siz 3-55
rom_a_we 3-56
rom_b_64 3-58
ROM_B_BASE 3-57
rom_b_en 3-58
rom_b_rv 3-58
rom_b_siz 3-58
rom_b_we 3-59
Row Address 3-53
rwcb 3-46
S
SBC mode 1-11
SBE_COUNT 3-51
scb0,scb1 3-52
scien 3-48
scof 3-51
scrub counter 3-52
Scrub Write Enable control bit 3-52
Scrub/Refresh Register
SMC 3-52
SDRAM
block organization 3-9
connections (block diagram) 3-4
Operational Method for Sizing 3-84
registers initializing 3-76
sizing 3-77
speed attributes 3-76
speeds 3-7
SDRAM Attributes Register
SMC 3-41
SDRAM Base Address Register
SMC 3-68
SDRAM Base Address/Enable 3-77
SDRAM Base Register
SMC 3-43
SDRAM Control Registers
Initialization Example 3-78
SDRAM Enable and Size Register
SMC 3-67
SDRAM Speed Attributes Register
SMC 3-69
Serial Presence Detect (SPD) 3-77
Serial Presence Detect (SPD) Definitions
1-12
sien 3-49
Single Bit Error Counter 3-51
single-beat reads/writes 3-6
single-bit error 3-12
single-bit errors ordered by syndrome code
3-88
sizing SDRAM 3-77
SMC
32-Bit Counter 3-73
address parity 3-10
Address Parity Error Address Register
3-72
Address Parity Error Log Register 3-71
cache coherency 3-11
CLK Frequency Register 3-44
CSR Accesses 3-34
cycle types 3-11
data parity 3-10
Data Parity Error Upper Data Register
3-62
data transfers 3-9
ECC Control Register 3-46
Error Address Register 3-52
error correction 3-11
Error Logger Register 3-50
error logging 3-13
External Register Set 3-34
General Control Register 3-39
Hawk 1-4
L2 cache support 3-11
on Hawk 3-1
refresh/scrub 3-34
ROM A Base/Size Register 3-54
ROM B Base/Size Register 3-57
ROM Speed Attributes Register 3-59
Scrub/Refresh Register 3-52
SDRAM Base Address Register 3-43,
3-68
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