MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
I 2 C Interface
The ASIC has an I 2 C (Inter-Integrated Circuit) two-wire serial interface
bus: Serial Clock Line (SCL) and Serial Data Line (SDA). This interface
has master-only capability and may be used to communicate the
configuration information to a slave I 2 C device such as serial EEPROM.
The I 2 C interface is compatible with these devices, and the inclusion of a
serial EEPROM in the memory subsystem may be desirable. The
EEPROM could maintain the configuration information related to the
memory subsystem even when the power is removed from the system.
Each slave device connected to the I 2 C bus is software addressable by a
unique address. The number of interfaces connected to the I 2 C bus is solely
dependent on the bus capacitance limit of 400pF.
For I 2 C bus programming, the ASIC is the only master on the bus and the
serial EEPROM devices are all slaves. The I 2 C bus supports 7-bit
addressing mode and transmits data one byte at a time in a serial fashion
with the most significant bit (MSB) being sent out first. Five registers are
required to perform the I 2 C bus data transfer operations. These are the I 2 C
Clock Prescaler Register, I 2 C Control Register, I 2 C Status Register, I 2 C
Transmitter Data Register, and I 2 C Receiver Data Register.
The I 2 C SDA is an open-drain bi-directional line on which data can be
transferred at a rate up to 100 Kbits/s in the standard mode, or up to 400
kbits/s in the fast mode. The I 2 C serial clock (SCL) is programmable via
I2_PRESCALE_VAL bits in the I 2 C Clock Prescaler Register. The I 2 C
clock frequency is determined by the following formula:
I 2 C CLOCK = SYSTEM CLOCK / (I2_PRESCALE_VAL+1) / 2
The I 2 C bus has the ability to perform byte write, page write, current
address read, random read, and sequential read operations.
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