MVME5100 Single Board Computer Programmer's Reference Guide

Software Considerations
8. Now that at least one refresh has occurred since SDRAM was last
accessed, it is okay to write to the SDRAM control registers.
a. Program the SDRAM Speed Attributes Register using the
information obtained in steps 3 and 4 and the fact that the
swr_dp and tdp bits should be set to 1’s.
b. Program the SDRAM Base Address Register (Blocks A/B/C/D)
and the SDRAM Base Address Register (Blocks E/F/G/H). Each
block’s base address should be programmed so that it is an even
multiple of its size. (The size information was obtained in step
5). If the isa_hole bit is to be set this may be a good time to do
that also. Refer to the Revision ID/General Control Register
section for more information.
c. Program the SDRAM Enable and Size Register (Blocks
A,B,C,D) and the SDRAM Enable and Size Register (Blocks
E,F,G,H). Use the information from step 5 for this. Only those
blocks that exist should be enabled. Also, only those that exist
should be programmed with a non-zero size.
9. Wait for at least one SDRAM refresh to complete. A simple way to
do this is to wait for the 32-bit counter to increment at least 100
times (refer to the section on the 32-Bit Counter for more
information). Note that the refdis control bit must not be set in the
ECC Control Register.
10. SDRAM is now ready to use.
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