MVME5100 Single Board Computer Programmer's Reference Guide

Cache Coherency
Functional Description
The SMC supports cache coherency to SDRAM only. It does this by
monitoring the ARTRY_ control signal on the PPC60x bus and behaving
appropriately when it is asserted. When ARTRY_ is asserted, if the access
is a SDRAM read, the SMC does not source the data for that access. If the
access is a SDRAM write, the SMC does not write the data for that access.
Depending upon when the retry occurs, the SMC may cycle the SDRAM
even though the data transfer does not happen.
Cache Coherency Restrictions
L2 Cache Support
SDRAM ECC
Cycle Types
The PPC60x GBL_ signal must not be asserted in the CSR areas.
The SMC provides support for a look-aside L2 cache (only at 66.67 MHz)
by implementing a hold-off input, L2CLM_. On cycles that select the
SMC, the SMC samples L2CLM_ on the second rising edge of the CLK
input after the assertion of TS_. If L2CLM_ is high, the SMC responds
normally to the cycle. If it is low, the SMC ignores the cycle.
The SMC performs single-bit error correction and double-bit error
detection for SDRAM across 64 bits of data using 8 check bits. No
checking is provided for ROM/Flash.
To support ECC, the SMC always deals with SDRAM using full width
(72-bit) accesses. When the PPC60x bus master requests any size read of
SDRAM, the SMC reads the full width at least once. When the PPC60x
bus master requests a four-beat write to SDRAM, the SMC writes all 72
bits four times. When the PPC60x bus master requests a single-beat write
to SDRAM, the SMC performs a full width read cycle to SDRAM, merges
in the appropriate PPC60x bus write data, and writes full width back to
SDRAM.
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