MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
Optional Method for Sizing SDRAM
Generally SDRAM block sizes can be determined by using SPD
information (refer to the previous section on SDRAM Control Registers
Initialization example). Another method for accomplishing this is as
follows:
1. Initialize the SMC’s control register bits to a known state.
a. Clear the isa_hole bit (refer to the section titled Vendor/Device
Register for more information.)
b. Make sure the CLK Frequency Register matches the operating
frequency.
c. Wait for at least one SDRAM refresh to complete. A simple way
to do this is to wait for the 32-bit counter to increment at least
100 times (refer to the section on 32-Bit Counter for more
information). Note that the refdis control bit must not be set in
the ECC Control Register.
d. Make sure that the SDRAM Speed Attributes Register contains
its power-up reset values. If not, make sure that the values match
the actual characteristics of the SDRAM being used.
e. Make sure the following bits are initialized as follows:
refdis = 0
rwcb = 0
derc = 1
scien = 0
dpien = 0
sien = 0
mien = 0
mbe_me = 0
SCRUB_FREQUENCY = $00
(Refer to the ECC Control Register section and the
Scrub/Refresh Register section for more information).
f. Make sure that ROM/Flash banks A and B are not enabled to
respond in the range $00000000 - $20000000. (Refer to the
section on ROM A Base/Size Register and ROM B Base/Size
Register for more information.)
g. Make sure that no other devices are set up to respond in the range
$00000000 - $20000000.
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